US5343066A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device and method of manufacturing same
Assignee: Sony Corp
•
Filing: 1993-03-18
•
Granted: 1994-08-30
•
Expires: 2013-03-18
Abstract
Abstract In a semiconductor device having a thin film transistor in which a gate insulator film and a semiconductor layer are formed on a gate electrode layer, and a portion of the semiconductor layer is connected to a specific gate electrode layer through a contact hole formed in the gate insulator film, a static random access memory is constituted by memory cells in each of which a conductive layer stacked on the upper layer side of the semiconductor layer through an insulator layer is inserted in the contact hole formed in the gate insulator film, and the portion of the semiconductor layer is electrically connected to the specific gate electrode layer through the conductive layer.
Inventors
- 👤 Yutaka Okamoto
- 👤 Makoto Yamada
- 👤 Masataka Shinguu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:51
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
128 words
A semiconductor device, comprising: a thin film transistor formed by a gate insulator film stacked on a first gate electrode layer and a semiconductor layer stacked on the gate insulator film; a portion of said semiconductor layer being electrically connected by a conductive layer to a second gate electrode layer through a contact hole formed in said gate insulator layer; and an insulator layer inserted between a portion of said conductive layer and said semiconductor layer; and said thin film transistor comprising a load transistor of a SRAM memory cell, one end of said semiconductor layer merging into a power supply line connected to said load transistor, and an additional conductive layer portion arranged over said power supply line comprising a shunt line of the power supply line.
Claim 2
Dependent Claim
128 words
A semiconductor device, comprising: a thin film transistor formed by a gate insulator film stacked on a first gate electrode layer and a semiconductor layer stacked on the gate insulator film; a portion of said semiconductor layer being electrically connected by a conductive layer to a second gate electrode layer through a contact hole formed in said gate insulator layer; and an insulator layer inserted between a portion of said conductive layer and said semiconductor layer; and said thin film transistor comprising a load transistor of a SRAM memory cell, one end of said semiconductor layer merging into a power supply line connected to said load transistor, and an additional conductive layer portion arranged over said power supply line comprising a shunt line of the power supply line.
References Cited (Backward Citations)
US5194749A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-29 | 1998-02-28 | 1998-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-29 | 2002-02-28 | 2002-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-29 | 2006-02-28 | 2006-08-30 | $7700.00 | Window Closed / Lapsed |