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US5343060A Expired / Lapsed US ⏱️ 0.0 years remaining

Apparatus for reducing mirror in a solid state imaging device wherein a light intercepting layer shields a transfer means from instant light and has an edge which slopes toward the light sensing region

Assignee: Sony Corp
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Filing: 1993-01-21
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Granted: 1994-08-30
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Expires: 2013-01-21
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Abstract

Abstract The present invention is directed to a solid state imaging deice in which a light sensing region (3), a vertical register (4) and a channel stopper region (5) are formed within a well region (2) on an N-type silicon substrate (1). A positive electric charge storage region (6) is formed on the surface of the light sensing region (3) and a well region (7) is formed beneath the vertical register (4), respectively. Further, a transfer electrode (9) is selectively formed on the vertical register (4) through a gate insulating layer (8) and an Al light-intercepting layer (11) is formed on the transfer electrode (9) through an interlevel insulator (10). A surface protecting layer (12) is formed on the whole surface including the Al light-intercepting layer (11). In this solid state imaging device, a tapered portion (11a) is formed on the Al light-intercepting layer 11 corresponding to a peripheral edge portion of the light sensing region 3. An oblique light component in an incident light and a reflected light component are suppressed from being introduced into the vertical register (4) to thereby reduce a smear.

Inventors

  • 👤 Hideshi Abe

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 03:07
CPC Classifications
H; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/15; H10F39/153; H10D; H10D44/00; H10D44/40; H10D44/45; H10D44/452

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 106 words
A solid state imaging device comprising: a semiconductor substrate; a light sensing region formed on said semiconductor substrate; a transfer means formed on said semiconductor substrate and formed adjacent to said light sensing region; a light intercepting means for shielding said transfer means from incident light having an edge which has a narrow portion on said light sensing region and which has an edge which sticks out toward said light sensing region and wherein said edge is tapered so that its end has a slope that extends downwardly toward said light sensing region, and a passivation layer covering said transfer means and said light sensing region.
Claim 2
Dependent Claim 106 words
A solid state imaging device comprising: a semiconductor substrate; a light sensing region formed on said semiconductor substrate; a transfer means formed on said semiconductor substrate and formed adjacent to said light sensing region; a light intercepting means for shielding said transfer means from incident light having an edge which has a narrow portion on said light sensing region and which has an edge which sticks out toward said light sensing region and wherein said edge is tapered so that its end has a slope that extends downwardly toward said light sensing region, and a passivation layer covering said transfer means and said light sensing region.
Claim 3
Dependent Claim 35 words
The solid state imaging device according to claim 1, wherein said transfer means comprises a transfer region formed on said semiconductor substrate and a transfer electrode arranged on said transfer region through an insulating layer.
Claim 4
Dependent Claim 22 words
The solid state imaging device according to claim 1, wherein said light intercepting means covers the side portion of said transfer means.
Claim 5
Dependent Claim 23 words
The solid state imaging device according to claim 1, wherein said passivation layer is formed of either a silicon nitride or silicon oxide.
Claim 6
Dependent Claim 19 words
The solid state imaging device according to claim 1, wherein said light intercepting means consists of an aluminum layer.

References Cited (Backward Citations)

JPS58138187A Cited
US4696021A Cited
US4914493A Cited
JPS6344760A Cited
JPS6344761A Cited
JPH03242974A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-08-29 1998-02-28 1998-08-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-08-29 2002-02-28 2002-08-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-08-29 2006-02-28 2006-08-30 $7700.00 Window Closed / Lapsed

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