Bulk charge modulated device photocell with lateral charge drain

Claim 2

An image sensing device comprising: a semiconductor substrate of a first conductivity type; a semiconductor region of a second conductivity type formed in the substrate; a transistor channel of a first conductivity type formed in the semiconductor region, the transistor channel including a transistor gate well for charge carriers of the second conductivity type, the transistor gate well formed at a substantial depth from the surface of the transistor, the charge carriers formed responsive to incident light; a source region of a first conductivity type formed in said semiconductor region and surrounded by the transistor channel, the source region operable to sense a change in threshold voltage of the transistor channel responsive to the collection of the charge carriers in the transistor gate well; a transistor drain region of the first conductivity type formed in the semiconductor region surrounding the transistor channel, the transistor drain region creates a virtual well in the semiconductor region for collecting the charge carriers during charge integration; a clear gate barrier region formed in the semiconductor region adjacent the virtual well; and a clear drain region of the second conductivity type formed in the semiconductor region adjacent the clear gate barrier region, the clear drain region operable to clear the charge carriers from the transistor gate well and the virtual well.

Claim 3

The device of claim 1, further comprising: an insulator region formed over the surface of the semiconductor region; and a transistor gate electrode formed over the insulator region and overlying the transistor channel.

Claim 4

The device of claim 2, further comprising a clear gate electrode formed over the insulator region and overlying the clear gate barrier region.

Claim 5

The device of claim 3, further comprising acceptor implants in the semiconductor region below the clear gate electrode.

Claim 6

The device of claim 1, further comprising donor implants in the semiconductor region below the transistor drain region.

Claim 7

The device of claim 1, further comprising a first conductive contact coupled to the transistor source region and a second conductive contact coupled to the clear drain region.

Claim 8

A semiconductor image sensor element comprising: a transistor gate potential well; a virtual potential well adjacent the transistor gate potential well; a clear gate barrier adjacent the virtual potential well; a clear drain adjacent the clear gate barrier; a charge sensor for sensing charge levels in the transistor gate potential well, the charge levels responsive to light incident on the device, whereby charge is stored in the virtual potential well during charge integration, after charge integration, the charge is transferred into the transistor gate potential well from the virtual potential well for charge detection by the charge sensor, and, after charge detection, the charge is transferred from the transistor gate potential well to the clear drain.

Claim 9

A semiconductor image sensor element comprising: a transistor gate potential well; a virtual potential well adjacent the transistor gate potential well; a clear gate barrier adjacent the virtual potential well; a clear drain adjacent the clear gate barrier; a charge sensor for sensing charge levels in the transistor gate potential well, the charge levels responsive to light incident on the device, whereby charge is stored in the virtual potential well during charge integration, after charge integration, the charge is transferred into the transistor gate potential well from the virtual potential well for charge detection by the charge sensor, and, after charge detection, the charge is transferred from the transistor gate potential well to the clear drain.

Claim 10

An image sensing device comprising: a semiconductor substrate of a first conductivity type; a first semiconductor layer of a second conductivity type in the substrate; a transistor drain region of the first conductivity type formed in the semiconductor layer, the transistor drain region forming a virtual well for carriers of the second conductivity type; a transistor source region of a first conductivity type formed in the semiconductor layer and spaced apart from the transistor drain region and surrounded by the transistor drain region; a clear drain region of a second conductivity type formed in the semiconductor layer and spaced apart from the transistor drain region and on the opposite side of the transistor drain region than the transistor source region; an insulating layer on the semiconductor layer; a transistor gate electrode formed on the insulating layer, the transistor gate electrode is located above a portion of the semiconductor region that surrounds the transistor source region and is surrounded by the transistor drain region, the transistor gate electrode forming a transistor gate potential well for carriers of the second conductivity type; a clear gate electrode formed on the insulating layer, the clear gate electrode is located above a portion of the semiconductor region that is between the transistor drain region and the clear drain region, the clear gate electrode forming a clear gate barrier between the transistor drain region and the clear drain region.

Claim 11

An image sensing device comprising: a semiconductor substrate of a first conductivity type; a first semiconductor layer of a second conductivity type in the substrate; a transistor drain region of the first conductivity type formed in the semiconductor layer, the transistor drain region forming a virtual well for carriers of the second conductivity type; a transistor source region of a first conductivity type formed in the semiconductor layer and spaced apart from the transistor drain region and surrounded by the transistor drain region; a clear drain region of a second conductivity type formed in the semiconductor layer and spaced apart from the transistor drain region and on the opposite side of the transistor drain region than the transistor source region; an insulating layer on the semiconductor layer; a transistor gate electrode formed on the insulating layer, the transistor gate electrode is located above a portion of the semiconductor region that surrounds the transistor source region and is surrounded by the transistor drain region, the transistor gate electrode forming a transistor gate potential well for carriers of the second conductivity type; a clear gate electrode formed on the insulating layer, the clear gate electrode is located above a portion of the semiconductor region that is between the transistor drain region and the clear drain region, the clear gate electrode forming a clear gate barrier between the transistor drain region and the clear drain region.

Claim 12

The device of claim 8 further comprising donor implants in the semiconductor layer below the transistor drain region.

Claim 13

The device of claim 8 further comprising acceptor implants in the semiconductor layer below the clear gate electrode.

Claim 14

The device of claim 8 wherein charge level in the transistor gate potential well is sensed by the transistor source region.

Claim 15

The device of claim 8 wherein charge is transferred from one potential area to another potential area by changing the voltages on the clear gate electrode and the transistor gate electrode.

Claim 16

The device of claim 8 wherein the clear gate electrode is coupled to the clear drain region.

Claim 17

The device of claim 8 further comprising a CMOS device in the semiconductor substrate spaced apart from the image sensing device.

Claim 18

The device of claim 14 wherein the CMOS device comprises: a second semiconductor layer of a second conductivity type in the semiconductor substrate and spaced apart from the first semiconductor layer; a third semiconductor layer of a first conductivity type in the second semiconductor layer; a first MOS transistor in the second semiconductor layer; a second MOS transistor in the third semiconductor layer connected to the first MOS transistor to form CMOS transistors.

Claim 19

The device of claim 15 further comprising a first voltage source region in the second semiconductor layer and a second voltage source region in the third semiconductor layer such that a voltage source having a first polarity can be connected to the second semiconductor layer and a second voltage source having a second polarity can be connected to the third semiconductor layer.