US5339402A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for connecting an IC memory card to a central processing unit of a computer
Assignee: Rhythm Co Ltd
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Filing: 1992-07-28
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Granted: 1994-08-16
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Expires: 2012-07-28
Abstract
Abstract An address storing device is provided for storing segment addresses based on data applied from a CPU. An IC memory card set in a computer is addressed with a low-order 8 bits address applied from the CPU. In accordance with a memory request signal and a read/write signal from the CPU, a chip enable signal, and a data enable signal are applied to the IC memory card, thereby reading data stored in the IC memory card by the CPU.
Inventors
- 👤 Tetsushi Ueda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 01:20
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0653; G06F12/0684; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
267 words
A system for controlling transmission data between an IC memory card and a central processing unit (CPU) of a computer comprising: device designating means responsive to a designating instruction from the CPU for generating a plurality of device designating signals; operation control means, responsive to one of said device designating signals, for latching data applied from the CPU and for producing operation control signals dependent upon said latched data; address storing means responsive to another of said device designating signals for storing a plurality of data applied from the CPU as segment data, and responsive to one of said operation control signals for producing a plurality of said stored segment data; addressing means for arithmetically adding said segment data applied from said address storing means to high order bit signals of an offset address from the CPU to produce added address data, and for combining said added address data with low order bit signals of said offset address to produce an IC memory card address, whereby said addressing means produces a greater number of IC memory card addresses than a maximum value of said offset address; converter means responsive to memory instructions from the CPU for generating a memory read signal and a memory write signal; control signal generator means responsive to one of said operation control signals for applying IC memory card control signals to an IC memory card in response to said memory read signal, said memory write signal, and an access instruction from the CPU; and data buffer means for allowing a bidirectional transmission of data between the IC memory card and the CPU.
Claim 2
Independent Claim
267 words
A system for controlling transmission data between an IC memory card and a central processing unit (CPU) of a computer comprising: device designating means responsive to a designating instruction from the CPU for generating a plurality of device designating signals; operation control means, responsive to one of said device designating signals, for latching data applied from the CPU and for producing operation control signals dependent upon said latched data; address storing means responsive to another of said device designating signals for storing a plurality of data applied from the CPU as segment data, and responsive to one of said operation control signals for producing a plurality of said stored segment data; addressing means for arithmetically adding said segment data applied from said address storing means to high order bit signals of an offset address from the CPU to produce added address data, and for combining said added address data with low order bit signals of said offset address to produce an IC memory card address, whereby said addressing means produces a greater number of IC memory card addresses than a maximum value of said offset address; converter means responsive to memory instructions from the CPU for generating a memory read signal and a memory write signal; control signal generator means responsive to one of said operation control signals for applying IC memory card control signals to an IC memory card in response to said memory read signal, said memory write signal, and an access instruction from the CPU; and data buffer means for allowing a bidirectional transmission of data between the IC memory card and the CPU.
Claim 3
Dependent Claim
30 words
A system for controlling transmission data in accordance with claim 1, wherein said designating instruction and said access instruction are signals selected from the address signals of the CPU, respectively.
Claim 4
Dependent Claim
32 words
A system for controlling transmission data in accordance with claim 1, wherein the memory instructions applied to the converter means include a memory request signal and a read/write signal of the CPU.
Claim 5
Dependent Claim
21 words
A system for controlling transmission data in accordance with claim 1, wherein the operation control means includes an operation control buffer.
Claim 6
Dependent Claim
59 words
A system for controlling transmission data in accordance with claim 1, wherein the control signal generator means comprises a memory decoder responsive to an instruction of the CPU and a control signal buffer responsive to an output of the memory decoder and the operation signal for generating a chip enable signal, a data enable signal and a write signal.
Claim 7
Dependent Claim
19 words
A system for controlling transmission data in accordance with claim 1, the converter means comprises a logical gate circuit.
Claim 8
Dependent Claim
21 words
A system for controlling transmission data in accordance with claim 1, wherein said designating instruction includes a strobe and address signal.
Claim 9
Dependent Claim
28 words
A system for controlling transmission data in accordance with claim 1, wherein said IC memory card control signals include a chip enable signal and a data enable signal.
Claim 10
Dependent Claim
27 words
A system for controlling transmission data in accordance with claim 1, wherein said IC memory card control signals include a chip enable signal and a write signal.
Claim 11
Dependent Claim
37 words
A system for controlling transmission data in accordance with claim 1, further including detector means for detecting the connection of an IC memory card and for indicating the connection of an IC memory card to the CPU.
Claim 12
Dependent Claim
25 words
A system for controlling transmission data in accordance with claim 1, further including power supply means for supplying electric energy to the IC memory card.
Claim 13
Independent Claim
200 words
A system for controlling transmission data between an IC memory card and a central processing unit (CPU) of a computer comprising: device designating means responsive to a designating instruction from the CPU for generating a device designating signal; address storing means responsive to said device designating signals for storing a plurality of data applied from the CPU as segment data, and for producing a plurality of said stored segment data; addressing means for arithmetically adding said segment data applied from said address storing means to high order bit signals of an offset address from the CPU to produce added address data, and for combining said added address data with low order bit signals of said offset address to produce an IC memory card address, whereby said addressing means produces a greater number of IC memory card addresses than a maximum value of said offset address; converter means responsive to memory instructions from the CPU for regenerating a memory read signal and a memory write signal; and control signal generator means for applying IC memory card control signals to an IC memory card in response to said memory read signal, said memory write signal, and an access instruction from the CPU.
Claim 14
Independent Claim
200 words
A system for controlling transmission data between an IC memory card and a central processing unit (CPU) of a computer comprising: device designating means responsive to a designating instruction from the CPU for generating a device designating signal; address storing means responsive to said device designating signals for storing a plurality of data applied from the CPU as segment data, and for producing a plurality of said stored segment data; addressing means for arithmetically adding said segment data applied from said address storing means to high order bit signals of an offset address from the CPU to produce added address data, and for combining said added address data with low order bit signals of said offset address to produce an IC memory card address, whereby said addressing means produces a greater number of IC memory card addresses than a maximum value of said offset address; converter means responsive to memory instructions from the CPU for regenerating a memory read signal and a memory write signal; and control signal generator means for applying IC memory card control signals to an IC memory card in response to said memory read signal, said memory write signal, and an access instruction from the CPU.
Claim 15
Dependent Claim
30 words
A system for controlling transmission data in accordance with claim 12, wherein said designating instruction and said access instruction are signals selected from the address signals of the CPU, respectively.
Claim 16
Dependent Claim
32 words
A system for controlling transmission data in accordance with claim 12, wherein the memory instructions applied to the converter means include a memory request signal and a read/write signal of the CPU.
Claim 17
Dependent Claim
59 words
A system for controlling transmission data in accordance with claim 12, wherein the control signal generator means comprises a memory decoder responsive to an instruction of the CPU and a control signal buffer responsive to an output of the memory decoder and the operation signal for generating a chip enable signal, a data enable signal and a write signal.
Claim 18
Dependent Claim
19 words
A system for controlling transmission data in accordance with claim 12, the converter means comprises a logical gate circuit.
Claim 19
Dependent Claim
21 words
A system for controlling transmission data in accordance with claim 12, wherein said designating instruction includes a strobe and address signal.
Claim 20
Dependent Claim
28 words
A system for controlling transmission data in accordance with claim 12, wherein said IC memory card control signals include a chip enable signal and a data enable signal.
Claim 21
Dependent Claim
34 words
A system for controlling transmission data in accordance with claim 12, wherein said IC memory card control signals include a chip enable signal and a write signal, instruction includes an strobe and address signal.
Claim 22
Dependent Claim
37 words
A system for controlling transmission data in accordance with claim 12, further including detector means for detecting the connection of an IC memory card and for indicating the connection of an IC memory card to the CPU.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-15 | 1998-02-14 | 1998-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-15 | 2002-02-14 | 2002-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-15 | 2006-02-14 | 2006-08-16 | $7700.00 | Window Closed / Lapsed |