US5339345A
Expired / Lapsed
US
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Frequency divider circuit
Assignee: Samsung Electronics Co Ltd
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Filing: 1992-08-31
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Granted: 1994-08-16
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Expires: 2012-08-31
Abstract
Abstract A frequency divider state machine synchronously divides an input clock's frequency by 1.5. The clock divider circuit includes two storage elements which are clocked on different edges of the input clock signal. The outputs of the two storage elements are combined together using combinatorial logic, the results of which are provided back to the inputs of the two storage elements. Further, the two outputs of the memory storage elements are combined together to provide the desired output frequency. Preferably, the circuit is designed such that if either of the two memory storage elements powers up in an undesired state, the divide by 1.5 circuit will automatically transition to one of the desired states and continue to provide the output frequency at the desired divide by 1.5 clock frequency after the initial transition. The circuit can be implemented as a digital circuit in an ASIC, an LSI, or the like.
Inventors
- 👤 Lewis R. Mote, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:25
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/68
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
207 words
A logic circuit incorporated in a large scale integrated circuit that receives an input clock signal and generates an output clock signal with a frequency which is the frequency of the input clock signal divided by 1.5, comprising: a first storage element, said first storage element having a first data input, a first clock input and a first data output, said first storage element storing said first data input on occurrence of each rising edge of said input clock signal at said first clock input; a second storage element, said second storage element having a second data input, a second clock input, and a second data output, said second storage element storing said second data input on occurrence of each falling edge of said input clock signal at said second clock input; and combinatorial logic responsive to said first data output and said second data output to provide an output signal of said circuit, said output signal having a frequency which is the frequency of said input clock signal divided by 1.5, said combinational logic further providing a first input signal to said first data input of said first storage element and providing a second input signal to said second data input of said second storage element.
Claim 2
Dependent Claim
207 words
A logic circuit incorporated in a large scale integrated circuit that receives an input clock signal and generates an output clock signal with a frequency which is the frequency of the input clock signal divided by 1.5, comprising: a first storage element, said first storage element having a first data input, a first clock input and a first data output, said first storage element storing said first data input on occurrence of each rising edge of said input clock signal at said first clock input; a second storage element, said second storage element having a second data input, a second clock input, and a second data output, said second storage element storing said second data input on occurrence of each falling edge of said input clock signal at said second clock input; and combinatorial logic responsive to said first data output and said second data output to provide an output signal of said circuit, said output signal having a frequency which is the frequency of said input clock signal divided by 1.5, said combinational logic further providing a first input signal to said first data input of said first storage element and providing a second input signal to said second data input of said second storage element.
Claim 3
Dependent Claim
28 words
The circuit defined in claim 1, wherein said output signal, said first input signal and said second input signal generated by said combinatorial logic are the same signal.
Claim 4
Dependent Claim
31 words
The circuit as defined in claim 2, wherein said combinatorial logic comprises a single combinatorial logic gate to generate said output signal, said first input signal and said second input signal.
Claim 5
Dependent Claim
16 words
The circuit as defined in claim 3, wherein said single combinatorial logic gate is a NAND-gate.
Claim 6
Dependent Claim
26 words
The circuit as defined in claim 1, wherein said first input signal and said second input signal generated by said combinatorial logic are the same signal.
Claim 7
Dependent Claim
44 words
The circuit as defined in claim 5, wherein said combinatorial logic comprises first and second combinatorial logic gates, and wherein said combinatorial logic gate generates said first input signal and said second input signal and said second combinatorial logic gate generates said output signal.
Claim 8
Dependent Claim
25 words
The circuit as defined in claim 1, wherein said first input signal and said output signal generated by said combinatorial logic are the same signal.
Claim 9
Dependent Claim
45 words
The circuit as defined in claim 7, wherein said combinatorial logic comprises first and second combinatorial logic gates, and wherein said first combinatorial logic gate generates said first input signal and said output signal and said second combinatorial logic gate generates said second input signal.
Claim 10
Dependent Claim
19 words
The circuit as defined in claim 1, wherein said first storage element and said second storage element comprise D-flip-flops.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-15 | 1998-02-14 | 1998-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-15 | 2002-02-14 | 2002-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-15 | 2006-02-14 | 2006-08-16 | $7700.00 | Window Closed / Lapsed |