Combined decimation/interpolation filter for ADC and DAC

Claim 1

A decimation filter, comprising: (a) a first signal path consisting essentially of a high-speed delay element driving a high-speed-to-low-speed sampler driving at least one low speed delay element; (b) a second signal path consisting essentially of a high-speed-to-low-speed sampler driving an even number of taps, the taps including: (1) a first tap comprising a multiplier; and (2) an odd number of subsequent taps, each having a previous tap, and each comprising a multiplier, a low-speed delay element driven by the previous tap, and a summer driven by the multiplier and the delay element; the multiplier comprising means for simulating multiplication by shifting and varying an incoming signal according to primary primitives which are powers of two varied by one; the taps including a pair of middle taps, each middle tap having a tap weight equal to the tap weight of the other middle tap; each tap other than the middle taps having a tap symmetrical to it about the middle taps; each non-middle tap having a tap weight equal to the tap weight of its symmetrical tap; the sum of the delays of the second signal path being twice the delay of the first signal path; and the tap weights being selected to produce a half band low pass response; (c) means for summing outputs from the first and second signal paths; and (d) means for time domain multiplexing the summed outputs of the signal paths.