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US5338958A Expired / Lapsed US ⏱️ 0.0 years remaining

Semicondcutor device with high speed field effect transistor structure reducing concentrations of electric field near drain region

Assignee: NEC Corp
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Filing: 1993-01-28
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Granted: 1994-08-16
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Expires: 2013-01-28
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Abstract

Abstract A semiconductor device includes a MISFET which has a gate polysilicon between source and drain regions, the gate polysilicon being covered with a gate insulator film. The gate polysilicon with the gate insulator film thereon has a protruded curved bottom portion extending in the substrate direction. The source and drain regions have their respective bottom surfaces located above the location where the bottom of the gate insulator film is most protruded toward the substrate. At least the drain region has in the vicinity of the protruded bottom portion of the gate polysilicon, a sidewall portion having a bottom portion projecting laterally towards the protruded portion of the gate polysilicon and an upper portion bent into a concave shape to form a pocket between that upper portion and the gate insulator film.

Inventors

  • 👤 Hiroshi Mitsumoto

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 18:29
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/60; H10D64/00; H10D64/01; H10D64/025; H10D64/027

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 166 words
A semiconductor device comprising a MISFET which includes a gate polysilicon between a source region and a drain region, said gate polysilicon being covered with a gate insulator film, said gate polysilicon covered with said gate insulator film including a protruded, curved bottom portion extending in a direction of said substrate and into said substrate; said bottom portion having a curved surface and said gate insulator film having a most protruded part into said substrate; said source region and drain region each including a bottom surface located above said most protruded part of said gate insulator film; and at least said drain region including in the vicinity of a bottom thereof and around said protruded curved bottom portion of said gate polysilicon covered with said gate insulator film, a shaped sidewall portion including a lower portion protruding towards said bottom portion of said gate polysilicon and an upper portion of a concave shape to form a pocket between said upper portion and said gate insulator film.
Claim 2
Dependent Claim 166 words
A semiconductor device comprising a MISFET which includes a gate polysilicon between a source region and a drain region, said gate polysilicon being covered with a gate insulator film, said gate polysilicon covered with said gate insulator film including a protruded, curved bottom portion extending in a direction of said substrate and into said substrate; said bottom portion having a curved surface and said gate insulator film having a most protruded part into said substrate; said source region and drain region each including a bottom surface located above said most protruded part of said gate insulator film; and at least said drain region including in the vicinity of a bottom thereof and around said protruded curved bottom portion of said gate polysilicon covered with said gate insulator film, a shaped sidewall portion including a lower portion protruding towards said bottom portion of said gate polysilicon and an upper portion of a concave shape to form a pocket between said upper portion and said gate insulator film.

References Cited (Backward Citations)

US4680603A Cited
JPH02110973A Cited
JPH02153572A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-08-15 1998-02-14 1998-08-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-08-15 2002-02-14 2002-08-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-08-15 2006-02-14 2006-08-16 $7700.00 Window Closed / Lapsed

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