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US5338703A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for producing a recessed gate field effect transistor

Assignee: Mitsubishi Electric Corp
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Filing: 1993-07-07
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Granted: 1994-08-16
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Expires: 2013-07-07
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Abstract

Abstract In a method for producing a recessed gate field effect transistor including a recess in a semiconductor substrate and a gate electrode disposed in the recess, a photoresist film is applied to the semiconductor substrate and source and drain electrodes on the substrate, a first insulating film is formed on the photoresist film, a resist pattern, which has an opening for processing the first insulating film and the photoresist film are etched using the resist pattern as a mask to form an opening having a width increasing in the direction of the substrate, a second insulating film is formed on opposite side walls of the opening, the semiconductor substrate is etched using the opening narrowed by the second insulating film in the substrate to form a recess, the second insulating film is selectively removed by etching, gate metal is deposited on the photoresist and on the substrate in the recess, and unnecessary gate metal is removed by lifting-off the resist film.

Inventors

  • 👤 Hiroshi Matsuoka

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 12:05
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10P; H10P76/00; H10P76/40; H10P76/408; H10P76/4085; Y; Y10; Y10S; Y10S148/00; Y10S148/161

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 184 words
A method for producing a recessed gate field effect transistor including a recess in a semiconductor substrate and a gate electrode disposed in the recess comprising: applying a photoresist film to a surface of a semiconductor substrate and to source and drain electrodes on the semiconductor substrate; forming a first insulating film on said photoresist film; forming a resist pattern having an opening on said first insulating film; etching said first insulating film and said photoresist film to form an opening having a width increasing in the direction of said semiconductor substrate using said resist pattern as a mask; forming a pair of side walls comprising a second insulating film in and at opposite sides of the opening in said first insulating film and said photoresist film; forming a recess by etching said semiconductor substrate using the opening narrowed by said side walls as a mask; selectively removing said side walls by etching; depositing gate metal on said first insulating film and on said semiconductor substrate in the recess to form a gate electrode; and removing unnecessary gate metal by dissolving said photoresist film.
Claim 2
Independent Claim 184 words
A method for producing a recessed gate field effect transistor including a recess in a semiconductor substrate and a gate electrode disposed in the recess comprising: applying a photoresist film to a surface of a semiconductor substrate and to source and drain electrodes on the semiconductor substrate; forming a first insulating film on said photoresist film; forming a resist pattern having an opening on said first insulating film; etching said first insulating film and said photoresist film to form an opening having a width increasing in the direction of said semiconductor substrate using said resist pattern as a mask; forming a pair of side walls comprising a second insulating film in and at opposite sides of the opening in said first insulating film and said photoresist film; forming a recess by etching said semiconductor substrate using the opening narrowed by said side walls as a mask; selectively removing said side walls by etching; depositing gate metal on said first insulating film and on said semiconductor substrate in the recess to form a gate electrode; and removing unnecessary gate metal by dissolving said photoresist film.
Claim 3
Dependent Claim 25 words
The method for producing an FET of claim 1, wherein said first insulating film comprises silicon oxide and said second insulating film comprises silicon nitride.
Claim 4
Dependent Claim 24 words
The method for producing an FET of claim 1, wherein said photoresist film is one of PMGI (poly dimethyl glutarimide) and PMMA (poly methylmethacrylate).
Claim 5
Dependent Claim 17 words
The method for producing an FET of claim 3, wherein said second insulating film comprises silicon nitride.
Claim 6
Dependent Claim 26 words
The method for producing an FET of claim 1, wherein photo-assisted CVD is employed to form said second insulating film as a pair of side walls.
Claim 7
Dependent Claim 17 words
The method for producing an FET of claim 5, wherein said second insulating film comprises silicon nitride.
Claim 8
Independent Claim 125 words
A method for producing an FET comprising: forming a dummy gate on a semiconductor substrate on which source and drain electrodes are present; forming side walls comprising first insulating film on both sides of and contacting said dummy gate; applying a photoresist film to said substrate covering said source and drain electrodes and said dummy gate; treating said photoresist film to expose part of said side walls; selectively removing said dummy gate by etching, leaving an opening between said side walls; forming a recess by etching said semiconductor substrate through the opening; selectively removing said side walls by etching; depositing gate metal on said resist film and in the recess to form a gate electrode; and removing unnecessary gate metal by dissolving said resist film.
Claim 9
Independent Claim 125 words
A method for producing an FET comprising: forming a dummy gate on a semiconductor substrate on which source and drain electrodes are present; forming side walls comprising first insulating film on both sides of and contacting said dummy gate; applying a photoresist film to said substrate covering said source and drain electrodes and said dummy gate; treating said photoresist film to expose part of said side walls; selectively removing said dummy gate by etching, leaving an opening between said side walls; forming a recess by etching said semiconductor substrate through the opening; selectively removing said side walls by etching; depositing gate metal on said resist film and in the recess to form a gate electrode; and removing unnecessary gate metal by dissolving said resist film.
Claim 10
Dependent Claim 24 words
The method for producing an FET of claim 7, wherein said dummy gate comprises silicon nitride and said first insulating film comprises silicon oxide.
Claim 11
Dependent Claim 34 words
The method for producing an FET of claim 7, wherein said dummy gate comprises a refractory metal including removing said dummy gate by etching with a mixture of SF 6 and CHF 3 .
Claim 12
Dependent Claim 25 words
The method for producing an FET of claim 7, wherein said dummy gate comprises Al including removing said dummy gate by etching with hydrochloric acid.
Claim 13
Dependent Claim 39 words
The method for producing an FET of claim 7, including applying said photoresist film with an opening wider than said dummy gate and treating said photoresist film by thermally reflowing said photoresist film to cover part of said walls.
Claim 14
Dependent Claim 72 words
The method for producing an FET of claim 7, wherein said step of forming the dummy gate includes: forming an Al film on a second insulating film; forming a super-fine photoresist mask on said Al film; etching said Al film using said super-fine photoresist mask to form a portion of said dummy gate; and completing said dummy gate formation by etching said second insulating film using said dummy gate as a mask.
Claim 15
Dependent Claim 38 words
The method for producing an FET of claim 7, including applying said photoresist film to cover said dummy gate and side walls and etching-back said photoresist film to expose part of said side walls and said dummy gate.

References Cited (Backward Citations)

JPS60100432A Cited
JPS6321877A Cited
JPS6390171A Cited
US4700462A Cited
JPS642372A Cited
JPS6424465A Cited
JPH01175772A Cited
US5190892A Cited
US5122387A Cited
JPH03239337A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-08-15 1998-02-14 1998-08-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-08-15 2002-02-14 2002-08-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-08-15 2006-02-14 2006-08-16 $7700.00 Window Closed / Lapsed

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