US5337166A
Expired / Lapsed
US
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Color signal transforming apparatus
Assignee: Fujifilm Business Innovation Corp
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Filing: 1993-02-12
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Granted: 1994-08-09
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Expires: 2013-02-12
Abstract
Abstract A color signal transforming apparatus of the type in which three or four input signals are each divided into higher bits and lower bits, and output signals are formed by calculating basic data obtained from the combinations of the higher bits and the combination of interpolation data obtained from the combinations of the higher bits and the lower bits. The color signal transforming apparatus comprises an address translation memory for receiving the combination of higher bits as an address signal and transforming the address signal to another address signal, correcting data storing unit for outputting a calculation signal for the lower bits in response to an address signal as the combination of the higher bits, and lower-bit correcting calculating unit for correcting the lower bits by using the output signal of the correcting data storing unit to remarkably reduce the total memory capacity required for a color signal transforming apparatus.
Inventors
- 👤 Hiroaki Ikegami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:16
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/46; H04N1/56; H04N1/60; H04N1/6027; H04N1/6016; H04N1/6022; H04N1/6025
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
156 words
A color signal transforming apparatus comprising: address transforming means for transforming an address signal of a combination of higher bits into another address signal; basic data color correction memory means for outputting basic data in response to the transformed address signal; lower-bit correcting means including; lower-bit correction data storing means for outputting data for lower-bit correction in response to the address signal of the combination of higher bits; and lower-bit correction calculating means for correcting the lower bits by using the output signal of said lower-bit correcting means; interpolation data generating means for generating a set of interpolation data on the basis of the transformed address signal output from said address transforming means and the combination of the corrected lower bits output from said lower-bit correcting means; and adder means for adding together the output signal of said color correction memory means and the output signals of said interpolation data generating means, thereby producing output signals.
Claim 2
Dependent Claim
156 words
A color signal transforming apparatus comprising: address transforming means for transforming an address signal of a combination of higher bits into another address signal; basic data color correction memory means for outputting basic data in response to the transformed address signal; lower-bit correcting means including; lower-bit correction data storing means for outputting data for lower-bit correction in response to the address signal of the combination of higher bits; and lower-bit correction calculating means for correcting the lower bits by using the output signal of said lower-bit correcting means; interpolation data generating means for generating a set of interpolation data on the basis of the transformed address signal output from said address transforming means and the combination of the corrected lower bits output from said lower-bit correcting means; and adder means for adding together the output signal of said color correction memory means and the output signals of said interpolation data generating means, thereby producing output signals.
Claim 3
Dependent Claim
69 words
The color signal transforming apparatus according to claim 1 wherein when said address transforming means receives an address signal corresponding to interpolation regions outside a closed solid consisting of planes around a color reproduction range of the output device or a closed hypersolid consisting of hyperplanes around the same, said address transforming means converges the transformed address output values on the surface of the closed solid or the closed
Claim 4
Dependent Claim
67 words
The color signal transforming apparatus according to claim 1 wherein said address transforming means performs an address transformation so that the output address signals corresponding to the received higher address signals of the adjacent interpolation regions to be integrated have qual output address values, and wherein said lower-bit correcting means performs a region processing for correcting the lower bits according to the integration of said interpolation regions.
Claim 5
Dependent Claim
107 words
The color signal transforming apparatus according to claim 1 wherein when an integrated region in the coordinates of color space is addressed, said lower-bit correction data storing means outputs lower-bit correction data for correcting the lower bits on the coordinate axis along which the regions are integrated and absolute-value correction data for correcting absolute values of on the lower bits of the remaining axes, which the absolute values are required as the result of said region integration, and wherein said lower-bit correction calculating means includes region control means for correcting the lower bits on the basis of the lower-bit correction data and the absolute value correction data.
Claim 6
Dependent Claim
51 words
The color signal transforming apparatus according to claim 4 wherein said region control means comprises a wired OR circuit which receives the lower bits to be added to the lower-bit correction data and an arithmetic circuit for receiving an output of said wired OR circuit and the absolute value correction data.
Claim 7
Dependent Claim
17 words
The color signal transfoz1ning apparatus according to claim 5 wherein said arithmetic circuit is a shift register.
Claim 8
Dependent Claim
17 words
The color signal transforming apparatus according to claim 5 wherein said arithmetic circuit is a multiplication circuit.
Claim 9
Dependent Claim
72 words
The color signal transforming apparatus according to claim 1 wherein said lower-bit correction data memory means outputs an inversion-correcting data instructing the inversion of the coordinate axis for correcting the lower bits when the transformed address values are converged on the surface of the closed solid or closed hyper solid, and said lower-bit correction calculating means comprises controller for controlling the inversion of the coordinate axis with reference to the inversion-correcting data.
Claim 10
Dependent Claim
35 words
The color signal transforming apparatus according to claim 8 wherein said controller comprises an invertor for inverting the data output from said region control means and an incrementor for incrementing the output of said invertor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |