US5337045A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pattern generator
Assignee: Toshiba Corp
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Filing: 1992-01-17
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Granted: 1994-08-09
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Expires: 2012-01-17
Abstract
Abstract A pattern generator includes a control unit, an address generation unit, and a data memory unit. The control unit has a plurality of control memories for storing information of the scanning order of addresses, the control unit outputting an address in accordance with the information stored in the control memories. The address generation unit has a plurality of address control memories for storing information used for controlling to generate addresses, the address control memories being provided in correspondence with the control memories, a data multiplexer for selecting and outputting the information outputted from the plurality of address control memories, and an address control unit for controlling to generate the addresses in accordance with the information outputted from the data multiplexer, the address generation unit outputting the addresses generated upon control by the address control unit. The data memory unit stores test pattern data to be supplied to an object to be measured, the data memory unit being accessed in accordance with the addresses outputted from the address generation unit, and outputting the test pattern data at the addresses.
Inventors
- 👤 Hisatoshi Shirasaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 19:39
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0421; G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31919; G01R31/31921; H04M; H04M3/00; H04M3/22; H04M3/24; H04M3/244
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
205 words
A pattern generator comprising: a control unit having a plurality of control memories for storing first information of the scanning order of addresses, said control unit outputting an address to an address generation unit, said address for accessing address control memories in accordance with said first information stored in said control memories; said address generation unit including, a plurality of said address control memories for storing second information which is used for controlling generation of addresses, said addresses for accessing a data memory unit, said second information corresponding to said first information stored in said control memories, a data multiplexer for selecting and outputting said second information outputted from said plurality of address control memories, and an address control unit for controlling generation of said addresses in accordance with said second information outputted from said data multiplexer, said address generation unit outputting said addresses generated upon control by said address control unit; and said data memory unit, coupled to an object to be measured, for storing test pattern data to be supplied to said object to be measured, said data memory unit being accessed in accordance with said addresses outputted from said address generation unit and outputting said test pattern data stored at said addresses.
Claim 2
Dependent Claim
205 words
A pattern generator comprising: a control unit having a plurality of control memories for storing first information of the scanning order of addresses, said control unit outputting an address to an address generation unit, said address for accessing address control memories in accordance with said first information stored in said control memories; said address generation unit including, a plurality of said address control memories for storing second information which is used for controlling generation of addresses, said addresses for accessing a data memory unit, said second information corresponding to said first information stored in said control memories, a data multiplexer for selecting and outputting said second information outputted from said plurality of address control memories, and an address control unit for controlling generation of said addresses in accordance with said second information outputted from said data multiplexer, said address generation unit outputting said addresses generated upon control by said address control unit; and said data memory unit, coupled to an object to be measured, for storing test pattern data to be supplied to said object to be measured, said data memory unit being accessed in accordance with said addresses outputted from said address generation unit and outputting said test pattern data stored at said addresses.
Claim 3
Dependent Claim
45 words
A pattern generator according to claim 1, wherein said address control unit of said address generation unit generates ones of consecutive addresses, branch address and return address, and loop start address and return address, in accordance with said second information outputted from said data multiplexer.
Claim 4
Dependent Claim
169 words
A pattern generator according to claim 1, wherein said control unit includes: said plurality of control memories; a data multiplexer for selecting and outputting first information outputted from said plurality of control memories; a pattern generation controller for processing data in accordance with said first information outputted from said data multiplexer and outputting an execution address determined from the data processing result; a jump address register for storing a jump address; a start address register for storing a start address; an address register for storing an address to be used for reading data from said control memories; an increment-by-1 circuit for outputting an address from said address register by incrementing the address by 1; an address stack memory for storing a return address of a sub-routine program; and an address multiplexer for selecting and outputting one of the addresses stored in said jump address register, said start address register, said increment-by-1 circuit, and said address stack memory, in accordance with the execution address outputted from said pattern generation controller.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |