Differential output stage with reduced idle current

Claim 2

A differential output stage for generating a differential signal across an external resistor in response to first and second input signal, each input signal having an amplitude, the differential output stage comprising: a forward node and a reverse node, the external resistor being connectable therebetween; a forward current source having a first non-inverting input, a first inverting input, and a forward source output, the first non-inverting input being connected to receive the first input signal, the first inverting input and the forward source output being connected to the forward node; a forward current sink having a second non-inverting input, a second inverting input, and a forward sink output, the second non-inverting input being connected to receive the first input signal, the second inverting input and the forward sink output being connected to the forward node; a reverse current source having a third non-inverting input, a third inverting input, and a reverse source output, the third non-inverting input being connected to receive the second input signal, the third inverting input and the reverse source output being connected to the reverse node; and a reverse current sink having a fourth non-inverting input, a fourth inverting input, and a reverse sink output, the fourth non-inverting input being connected to receive the second input signal, the fourth inverting input and the reverse sink output being connected to the reverse node; whereby the forward current source outputs an idle forward source current, the forward current sink inputs substantially all of the forward source current, the reverse current source outputs an idle reverse source current, and the reverse current sink inputs substantially all of the idle reverse source current when the amplitude of the first signal and the second signal is substantially equivalent, the forward current source outputs an increased forward source current, the reverse current source outputs a reduced reverse current, the forward current sink inputs a minority portion of the increased forward source current, and the reverse current sink inputs a majority of the increased forward source current and the reduced reverse source current when the difference between the amplitude of the first signal and the second signal is positive, and the forward current source outputs a reduced forward source current, the reverse current source outputs an increased reverse source current, the forward current sink inputs a majority portion of the increased reverse source current and the reduced forward source current, and the reverse current sink inputs the reduced reverse source current when the difference between the amplitude of the first signal and the second signal is negative.

Claim 3

The differential output stage of claim 1 wherein each of the forward current source, the reverse current source, the forward current sink and the reverse current sink comprises a differential amplifier.

Claim 4

The differential output stage of claim 2 wherein the differential amplifier comprises a unity-gain amplifier.

Claim 5

The differential output stage of claim 1 wherein the forward current source further comprises: a driver transistor stage that generates the idle forward source current, the increased forward source current, and the reduced forward source current; a source differential pair stage that is connected to the driver transistor stage, and that controls the driver transistor stage; a source slew rate stage that is connected to the driver transistor stage, and that increases the slew rate of the driver transistor stage; and a source compensation capacitor that is connected to the driver transistor stage and the source differential pair stage, and that prevents oscillation in the voltage at the forward node.

Claim 6

The differential output stage of claim 4 wherein the forward current sink further comprises: a sinking transistor stage that inputs the idle forward source current, the minority portion of the increased forward source current, and the reduced forward source current; a sinking differential pair stage that is connected to the sinking transistor stage, and that controls the sinking transistor stage; a sinking slew rate stage that is connected to the sinking transistor stage, and that increases the slew rate of the sinking transistor stage; and a sinking compensation capacitor that is connected to the sinking transistor stage and the sinking differential pair stage, and that prevents oscillation in the voltage at the forward node.

Claim 7

The differential output stage of claim 5 wherein the driver transistor stage comprises: a driver transistor stage connected to the forward node, the source differential pair stage, and the source compensation capacitor, the driver transistor having a channel width; and a source balancing transistor connected to the forward node, the source input slew rate stage, and the driver transistor.

Claim 8

The differential output stage of claim 6 wherein the sinking transistor stage comprises: a sinking transistor connected to the forward node, the sinking differential pair stage, and the sinking compensation capacitor, the sinking transistor having a channel width; and a sinking balancing transistor connected to the forward node, the sinking input slew rate stage, and the sinking transistor.

Claim 9

The differential output stage of claim 7 wherein the channel width of the driver transistor is approximately two to three times greater than the channel width of the sinking transistor.

Claim 10

A differential output stage for generating a differential signal across an external resistor in response to the difference in amplitude between a first signal and a second signal, the differential output stage comprising: a forward node and a reverse node, the external resistor being connectable therebetween; a forward current source connected to the first signal that outputs (i) an idle forward source current into the forward node when the amplitude of the first signal and the amplitude of the second signal are substantially equivalent, (i) an increased forward source between the amplitude of the first signal and the amplitude of the second signal is positive, and (iii) a reduced forward source current into the forward node when the difference between the amplitude of the first signal and the amplitude of the second signal is negative; a reverse current source connected to the second signal that outputs (i) and idle reverse source current into the reverse node when the amplitude of the first signal and the amplitude of the second signal are substantially equivalent, (ii) a reduced reverse source current when the difference between the amplitude of the first signal and the amplitude of the second signal is positive, and (iii) an increased reverse source current when the difference between the amplitude of the first signal and the amplitude of the second signal is negative; a forward current sink connected to the first signal that inputs (i) substantially all of the idle forward source current when the amplitude of the first signal and the amplitude of the second signal are substantially equivalent, (ii) a minority portion of the increased forward source current when the difference between the amplitude of the first signal and the amplitude of the second signal is positive, and (iii) a majority portion of the increased reverse source current and the reduced forward source current when the difference between the amplitude of the first signal and the amplitude of the second signal is negative; and a reverse current sink connected to the second signal that inputs (i) the idle reverse source current when the amplitude of the first signal and the amplitude of the second signal are substantially equivalent, (ii) a majority of the increased forward source current and the reduced reverse source current when the difference between the amplitude of the first signal and the amplitude of the second signal is positive, and (iii) a minority portion of the increased reverse source current when the difference between the amplitude of the first signal and the amplitude of the second signal is negative, wherein a positive portion of the difference signal is generated when a portion of the increased forward source current flow across the external resistor from the forward current source to the reverse current sink and a negative portion of the difference signal is generated when a portion of the increased reverse source current flows across the external resistor from the reverse current source to the forward current sink.

Claim 11

A differential output stage for generating a differential signal across an external resistor in response to the difference in amplitude between a first signal and a second signal, the differential output stage comprising: a forward node and a reverse node, the external resistor being connectable therebetween; a forward current source connected to the first signal that outputs (i) an idle forward source current into the forward node when the amplitude of the first signal and the amplitude of the second signal are substantially equivalent, (i) an increased forward source between the amplitude of the first signal and the amplitude of the second signal is positive, and (iii) a reduced forward source current into the forward node when the difference between the amplitude of the first signal and the amplitude of the second signal is negative; a reverse current source connected to the second signal that outputs (i) and idle reverse source current into the reverse node when the amplitude of the first signal and the amplitude of the second signal are substantially equivalent, (ii) a reduced reverse source current when the difference between the amplitude of the first signal and the amplitude of the second signal is positive, and (iii) an increased reverse source current when the difference between the amplitude of the first signal and the amplitude of the second signal is negative; a forward current sink connected to the first signal that inputs (i) substantially all of the idle forward source current when the amplitude of the first signal and the amplitude of the second signal are substantially equivalent, (ii) a minority portion of the increased forward source current when the difference between the amplitude of the first signal and the amplitude of the second signal is positive, and (iii) a majority portion of the increased reverse source current and the reduced forward source current when the difference between the amplitude of the first signal and the amplitude of the second signal is negative; and a reverse current sink connected to the second signal that inputs (i) the idle reverse source current when the amplitude of the first signal and the amplitude of the second signal are substantially equivalent, (ii) a majority of the increased forward source current and the reduced reverse source current when the difference between the amplitude of the first signal and the amplitude of the second signal is positive, and (iii) a minority portion of the increased reverse source current when the difference between the amplitude of the first signal and the amplitude of the second signal is negative, wherein a positive portion of the difference signal is generated when a portion of the increased forward source current flow across the external resistor from the forward current source to the reverse current sink and a negative portion of the difference signal is generated when a portion of the increased reverse source current flows across the external resistor from the reverse current source to the forward current sink.

Claim 12

The differential output stage of claim 9 wherein each of the forward current source, the reverse current source, the forward current sink and the reverse current sink further comprises a differential amplifier.

Claim 13

The differential output stage of claim 10 wherein the differential amplifier comprises a unity-gain amplifier.

Claim 14

A differential output stage for generating a differential signal across an external resistor in response to the difference in voltages between a first signal and a second signal, the differential output stage comprising: a forward node and a reverse node, the external resistor being connectable therebetween; a forward current source that generates a reverse current into the forward node in response to the voltage of the first signal and the voltage at the forward node; a reverse current source that generates a reverse current into the reverse node in response to the voltage of the second signal and the voltage at the reverse node; a forward current sink that sinks a first current from the forward node in response to the voltage of the first signal and the voltage at the forward node; a reverse current sink that sinks a second current from the reverse node in response to the voltage of the second signal and the voltage at the reverse node, whereby when the voltage of the first signal and the voltage of the second signal are substantially equivalent, the magnitude of the forward current is substantially equivalent to the magnitude of the first current, and the magnitude of the reverse current is substantially equivalent to the magnitude of the second current, thereby causing no current to flow across the external resistor, whereby when the difference between the voltage of the first signal and the voltage of the second signal is positive, the magnitude of the forward current is greater than the magnitude of the first current, and the magnitude of the reverse current is less than the magnitude of the second current, thereby causing a current to flow across the external resistor from the forward node to the reverse node, and whereby when the difference between the voltage of the first signal and the voltage of the second signal is negative, the magnitude of the forward current is less than the magnitude of the first current, and the magnitude of the reverse current is greater than the magnitude of the second current, thereby causing a current to flow across the external resistor from the reverse node to the forward node.

Claim 15

A differential output stage for generating a differential signal across an external resistor in response to the difference in voltages between a first signal and a second signal, the differential output stage comprising: a forward node and a reverse node, the external resistor being connectable therebetween; a forward current source that generates a reverse current into the forward node in response to the voltage of the first signal and the voltage at the forward node; a reverse current source that generates a reverse current into the reverse node in response to the voltage of the second signal and the voltage at the reverse node; a forward current sink that sinks a first current from the forward node in response to the voltage of the first signal and the voltage at the forward node; a reverse current sink that sinks a second current from the reverse node in response to the voltage of the second signal and the voltage at the reverse node, whereby when the voltage of the first signal and the voltage of the second signal are substantially equivalent, the magnitude of the forward current is substantially equivalent to the magnitude of the first current, and the magnitude of the reverse current is substantially equivalent to the magnitude of the second current, thereby causing no current to flow across the external resistor, whereby when the difference between the voltage of the first signal and the voltage of the second signal is positive, the magnitude of the forward current is greater than the magnitude of the first current, and the magnitude of the reverse current is less than the magnitude of the second current, thereby causing a current to flow across the external resistor from the forward node to the reverse node, and whereby when the difference between the voltage of the first signal and the voltage of the second signal is negative, the magnitude of the forward current is less than the magnitude of the first current, and the magnitude of the reverse current is greater than the magnitude of the second current, thereby causing a current to flow across the external resistor from the reverse node to the forward node.

Claim 16

The differential output stage of claim 12 wherein each of the forward current source, the reverse current source, the forward current sink and the reverse current sink further comprises a differential amplifier.

Claim 17

The differential output stage of claim 12 wherein the differential amplifier comprises a unity-gain amplifier.

Claim 18

The differential output stage of claim 12 wherein the first signal and the second signal are complementary signals.

Claim 19

The differential output stage of claim 9 wherein the first signal and the second signal are complementary signals.

Claim 20

The differential output stage of claim 1 wherein the first signal and the second signal are complementary signals.