FIFO based parity generator

Claim 2

A parity generator for generating a block of m parity bits from a series of K data blocks, each one of the K data blocks comprising a series of m bits, the parity generator comprising: an XOR logic device having first and second inputs and an output, the first input coupled to the K data blocks to receive one of the m bits; a parity bit storage device comprising a series of m one bit memory locations arranged as a FIFO data structure, the parity bit storage device having an output coupled to the second input of the XOR logic device and an input coupled to the output of the XOR logic device; a write/read address generator coupled to the storage device, the write/read address generator having a read control input and a write control input; the write control input adapted to receive a FIFO write signal that causes the write/read address generator to control the storage device to store a signal output by the XOR logic device, in the storage device in the FIFO manner, the signal comprising the logical result of XORing the first and second XOR inputs to provide a parity bit signal; the read control input adapted to receive a FIFO read signal that causes the write/read address generator to control the storage device to output the parity bit signal stored in the storage device, in the FIFO manner.

Claim 3

The parity generator of claim 1, further comprising a buffer coupled to the output of the parity bit storage device.

Claim 4

The parity generator of claim 2, further comprising a first latch coupling the K data blocks to the first input of the XOR logic device.

Claim 5

The parity generator of claim 3, further comprising a second latch coupling the output of the parity bit storage device to the second input of the XOR logic device and to the buffer.

Claim 6

The parity generator of claim 4, further comprising a third latch coupling the second latch to the buffer.

Claim 7

The parity generator of claim 5, further comprising a state machine for generating signals for enabling and de-enabling the first, second, and third latches.

Claim 8

The parity generator of claim 6, further comprising a bus coupling the K data blocks to the first input of the XOR logic device and to the third latch.

Claim 9

The parity generator of claim 5, further comprising a state machine for generating signals for enabling and de-enabling the first, second, and third latches and for asserting and de-asserting the FIFO write and FIFO read signals to cause each one of the m bits of the first K data block to be XORed with a logical zero output by the parity storage device.

Claim 10

A parity generator for generating a block of m parity bits from a series of K data blocks, each one of the K data blocks comprising a series of m bits, the m bits of each data block being arranged to form P words, each word having n bits, the parity generator including n circuits with each circuit comprising: an XOR logic device having first and second inputs and an output, the first input coupled to the P words of the K data blocks to receive one of the n bits; a parity bit storage device comprising a series of P one bit memory locations arranged as a FIFO data structure, the parity bit storage device having an output coupled to the second input of the XOR logic device and an input coupled to the output of the XOR logic device; a write/read address generator coupled to the storage device, the write/read address generator having a read control input and a write control input; the write control input adapted to receive a FIFO write signal that causes the write/read address generator to control the storage device to store a signal output by the XOR logic device, in the storage device in the FIFO manner, the signal comprising the logical result of XORing the first and second X0R inputs to provide a parity bit signal; the read control input adapted to receive a FIFO read signal that causes the write/read address generator to control the storage device to output the parity bit signal stored in the storage device, in the FIFO manner.

Claim 11

A parity generator for generating a block of m parity bits from a series of K data blocks, each one of the K data blocks comprising a series of m bits, the m bits of each data block being arranged to form P words, each word having n bits, the parity generator including n circuits with each circuit comprising: an XOR logic device having first and second inputs and an output, the first input coupled to the P words of the K data blocks to receive one of the n bits; a parity bit storage device comprising a series of P one bit memory locations arranged as a FIFO data structure, the parity bit storage device having an output coupled to the second input of the XOR logic device and an input coupled to the output of the XOR logic device; a write/read address generator coupled to the storage device, the write/read address generator having a read control input and a write control input; the write control input adapted to receive a FIFO write signal that causes the write/read address generator to control the storage device to store a signal output by the XOR logic device, in the storage device in the FIFO manner, the signal comprising the logical result of XORing the first and second X0R inputs to provide a parity bit signal; the read control input adapted to receive a FIFO read signal that causes the write/read address generator to control the storage device to output the parity bit signal stored in the storage device, in the FIFO manner.

Claim 12

The parity generator of claim 9, wherein each one of the n circuits further comprises a buffer coupled to the output of the parity bit storage device.

Claim 13

The parity generator of claim 10, wherein each one of the n circuits further comprises a first latch coupling the P words of the K data blocks to the first input of the XOR logic device.

Claim 14

The parity generator of claim 11, wherein each one of the n circuits further comprises a second latch coupling the output of the parity bit storage device to the second input of the XOR logic device and to the buffer.

Claim 15

The parity generator of claim 12, wherein each one of the n circuits further comprises a third latch coupling the second latch to the buffer.

Claim 16

The parity generator of claim 13, further comprising a state machine for generating signals for enabling and de-enabling the first, second, and third latches of the n circuits.

Claim 17

The parity generator of claim 14, further comprising a bus coupling the P words of the K data blocks to the first input of the XOR logic device and to the third latch of each one of the n circuits.

Claim 18

The parity generator of claim 13, further comprising a state machine for generating signals for enabling and de-enabling the first, second, and third latches of the n circuits and for asserting and de-asserting the FIFO write and FIFO read signals to cause each one of the n bits of the P words of the first K data block to be XORed with a logical zero output by the parity storage device of each one of the n circuits.

Claim 19

A parity generator for generating a block of m parity bits from a series of K data blocks, each one of the K data blocks comprising a series of m bits, the parity generator comprising: an XOR logic device including, a) a first input to receive a series of one bit parity -- block signals, b) a second input coupled to the K data blocks to receive a series of input signals each input signal comprising one of the series of m bits of data comprising one of the K data blocks, and c) a parity bit output for outputting a series of one bit parity signals generated by the XOR logic device by performing a logical XOR operation on each one of the parity -- block signals in the series of signals received by the first signal input, and each corresponding input signal in the series of input signals supplied to the second signal input of the XOR logic device; and a logic block comprising m one bit storage locations arranged in a FIFO data structure for storing the one bit parity signals output by the XOR logic device, the logic block includes a) a first input to receive a FIFO read enable signal, to enable the logic block to output one of m values stored in the logic block's m one bit storage locations as a function of the FIFO read enable signal and the FIFO data structure, b) a second input to receive a FIFO write enable signal, to enable the logic block to store the series of one bit parity signals output by the XOR logic device in one of the logic block's m one bit storage locations as a function of the FIFO write enable signal and the FIFO data structure, c) a parity bit input coupled to the parity bit output of the XOR logic device, and d) a parity -- block signal output coupled to the first input of the XOR logic device and for outputting the series of m one bit parity signals stored in the logic block's m one bit storage locations.

Claim 20

A parity generator for generating a block of m parity bits from a series of K data blocks, each one of the K data blocks comprising a series of m bits, the parity generator comprising: an XOR logic device including, a) a first input to receive a series of one bit parity -- block signals, b) a second input coupled to the K data blocks to receive a series of input signals each input signal comprising one of the series of m bits of data comprising one of the K data blocks, and c) a parity bit output for outputting a series of one bit parity signals generated by the XOR logic device by performing a logical XOR operation on each one of the parity -- block signals in the series of signals received by the first signal input, and each corresponding input signal in the series of input signals supplied to the second signal input of the XOR logic device; and a logic block comprising m one bit storage locations arranged in a FIFO data structure for storing the one bit parity signals output by the XOR logic device, the logic block includes a) a first input to receive a FIFO read enable signal, to enable the logic block to output one of m values stored in the logic block's m one bit storage locations as a function of the FIFO read enable signal and the FIFO data structure, b) a second input to receive a FIFO write enable signal, to enable the logic block to store the series of one bit parity signals output by the XOR logic device in one of the logic block's m one bit storage locations as a function of the FIFO write enable signal and the FIFO data structure, c) a parity bit input coupled to the parity bit output of the XOR logic device, and d) a parity -- block signal output coupled to the first input of the XOR logic device and for outputting the series of m one bit parity signals stored in the logic block's m one bit storage locations.

Claim 21

A parity generator for generating a block of parity bits from a series of K data blocks, each one of the K data blocks comprising a series of m bits, the parity generator comprising: i) a buffer including, a parity -- block signal input for receiving a series of parity -- block signals, b) a parity generator parity signal output for outputting a series of one bit parity signals, and c) an enable input to receive an output enable signal, to enable the parity generator parity signal output as a function of the output enable signal; ii) an XOR logic device including, a) a first input to receive a series of one bit parity -- block signals, b) a second input coupled to the K data blocks to receive a series of input signals, each one of the series of input signals comprising one of the series of m bits of data comprising one of the K data blocks, and c) a parity bit output for outputting a series of one bit parity signals generated by the XOR logic device by performing a logical XOR operation on each one of the parity -- block signals in the series of parity -- block signals received by the first signal input, and each corresponding input signal in the series of input signals supplied to the second signal input of the XOR logic device; and iii) a logic block comprising m one bit storage locations arranged in a FIFO data structure for storing the one bit parity signals output by the XOR logic device, the logic block includes a) a first input to receive a FIFO read enable signal, to enable the logic block to output one of m values stored in the logic block's m one bit storage locations as a function of the FIFO read enable signal and the FIFO data structure, b) a second input to receive a FIFO write enable signal, to enable the logic block to store the series of one bit parity signals output by the XOR logic device in one of the logic block's m one bit storage locations as a function of the FIFO write enable signal and the FIFO data structure, c) a parity bit input coupled to the parity bit output of the XOR logic device, and d) a parity -- block signal output coupled to the first input of the XOR logic device and to the parity -- block signal input of the buffer.

Claim 22

A parity generator for generating a block of parity bits from a series of K data blocks, each one of the K data blocks comprising a series of m bits, the parity generator comprising: i) a buffer including, a parity -- block signal input for receiving a series of parity -- block signals, b) a parity generator parity signal output for outputting a series of one bit parity signals, and c) an enable input to receive an output enable signal, to enable the parity generator parity signal output as a function of the output enable signal; ii) an XOR logic device including, a) a first input to receive a series of one bit parity -- block signals, b) a second input coupled to the K data blocks to receive a series of input signals, each one of the series of input signals comprising one of the series of m bits of data comprising one of the K data blocks, and c) a parity bit output for outputting a series of one bit parity signals generated by the XOR logic device by performing a logical XOR operation on each one of the parity -- block signals in the series of parity -- block signals received by the first signal input, and each corresponding input signal in the series of input signals supplied to the second signal input of the XOR logic device; and iii) a logic block comprising m one bit storage locations arranged in a FIFO data structure for storing the one bit parity signals output by the XOR logic device, the logic block includes a) a first input to receive a FIFO read enable signal, to enable the logic block to output one of m values stored in the logic block's m one bit storage locations as a function of the FIFO read enable signal and the FIFO data structure, b) a second input to receive a FIFO write enable signal, to enable the logic block to store the series of one bit parity signals output by the XOR logic device in one of the logic block's m one bit storage locations as a function of the FIFO write enable signal and the FIFO data structure, c) a parity bit input coupled to the parity bit output of the XOR logic device, and d) a parity -- block signal output coupled to the first input of the XOR logic device and to the parity -- block signal input of the buffer.

Claim 23

A parity generator for generating a block of m parity bits from a series of K data blocks, each one of the K data blocks comprising m bits arranged to form P words, each word having n bits the parity generator comprising: a bus comprising n lines coupled to the K data blocks; a plurality of n one bit parity generator circuits, each one of the n one bit parity generator circuits having an input and an output coupled to a respective one of the n lines of the bus, each one of the one bit parity generator circuits comprising, i) an XOR logic device including, a) a first input to receive a series of one bit parity -- block signals, b) a second input coupled to the input of the one bit parity generator circuit to receive a series of input signals from the respective line of the bus, each input signal comprising one of the series of n bits comprising one of the P words of data comprising one of the K data blocks, and c) a parity bit output for outputting the series of one bit parity signals generated by the XOR logic device by performing a logical XOR operation on each one of the parity -- block signals in the series of parity -- block signals received by the first signal input, and each corresponding input signal in the series of input signals supplied by the line of the bus to the second signal input of the XOR logic device; and ii) a logic block comprising P one bit storage locations arranged in a FIFO data structure for storing the one bit parity signals output by the XOR logic device, the logic block includes, a) a first input to receive a FIFO read enable signal, to enable the logic block to output one of P values stored in the logic block's P one bit storage locations as a function of the FIFO read enable signal and the FIFO data structure, b) a second input to receive a FIFO write enable signal, to enable the logic block to store the series of one bit parity signals output by the XOR logic device in one of the logic block's P one bit storage locations as a function of the FIFO write enable signal and the FIFO data structure, c) a parity bit input coupled to the parity bit output of the XOR logic device, and d) a parity -- block signal output coupled to the first input of the XOR logic device and coupled to the output of the one bit parity generator circuit.

Claim 24

A parity generator for generating a block of m parity bits from a series of K data blocks, each one of the K data blocks comprising m bits arranged to form P words, each word having n bits the parity generator comprising: a bus comprising n lines coupled to the K data blocks; a plurality of n one bit parity generator circuits, each one of the n one bit parity generator circuits having an input and an output coupled to a respective one of the n lines of the bus, each one of the one bit parity generator circuits comprising, i) an XOR logic device including, a) a first input to receive a series of one bit parity -- block signals, b) a second input coupled to the input of the one bit parity generator circuit to receive a series of input signals from the respective line of the bus, each input signal comprising one of the series of n bits comprising one of the P words of data comprising one of the K data blocks, and c) a parity bit output for outputting the series of one bit parity signals generated by the XOR logic device by performing a logical XOR operation on each one of the parity -- block signals in the series of parity -- block signals received by the first signal input, and each corresponding input signal in the series of input signals supplied by the line of the bus to the second signal input of the XOR logic device; and ii) a logic block comprising P one bit storage locations arranged in a FIFO data structure for storing the one bit parity signals output by the XOR logic device, the logic block includes, a) a first input to receive a FIFO read enable signal, to enable the logic block to output one of P values stored in the logic block's P one bit storage locations as a function of the FIFO read enable signal and the FIFO data structure, b) a second input to receive a FIFO write enable signal, to enable the logic block to store the series of one bit parity signals output by the XOR logic device in one of the logic block's P one bit storage locations as a function of the FIFO write enable signal and the FIFO data structure, c) a parity bit input coupled to the parity bit output of the XOR logic device, and d) a parity -- block signal output coupled to the first input of the XOR logic device and coupled to the output of the one bit parity generator circuit.

Claim 25

The parity generator of claim 19 wherein each one of the n one bit parity generator circuits further comprises a buffer including: a) a parity -- block signal input coupled to the parity -- block signal output of the logic block, for receiving the series of one bit parity -- block signals output by the logic block, b) an output coupled to the one bit parity generator circuit output for outputting the series of one bit parity -- block signals received by the buffer, and c) an enable input to receive an output enable signal to enable the output of the buffer as a function of the output enable signal.

Claim 26

The parity generator of claim 20 wherein each one of the n one bit parity generator circuits further comprises a first latch including: a) an input coupled to the one bit parity generator circuit's input to receive the series of input signals from the bus, b) a parity generator latch enable input for receiving an input latch enable signal enabling the first latch to store each one of the series of input signals received from the bus, sequentially, as a function of the input latch enable signal, and c) an output coupled to the second input of the XOR logic device for outputting each one of the series of input signals received from the line of the bus.

Claim 27

The parity generator of claim 21 wherein each one of the n one bit parity generator circuits further comprises a second latch including: a) a parity -- block signal input coupled to the logic block's parity -- block signal output to receive the series of one bit parity -- block signals output by the logic block, b) a latch enable input to receive a second -- latch enable signal, to enable the second latch to store each one of the series of one bit parity -- block signal output, sequentially, as a function of the c) an output coupled to the first input of the XOR logic device and the parity -- block signal input of the buffer for outputting the series of one bit parity -- block signals received from the logic block's data signal output.

Claim 28

A computer system, comprising: a bus comprising n data lines and a series of control lines; a data storage device coupled to the bus for storing a series of K data blocks, each data block comprising m bits arranged to form P words, each one of the P words comprising a series of n bits; a parity generator coupled to the bus for generating a block of m parity bits from the series of K data blocks, the parity generator comprising a plurality of n one bit parity generator circuits, each parity generator circuit comprising, i) an input and an output being coupled to a respective one of the n data lines of the bus, ii) an XOR logic device including, a) a first input to receive a series of one bit parity -- block signals, b) a second input coupled to the input of the one bit parity generator circuit to receive a series of input signals from the respective data line of the bus each input signal comprising a respective one of the series of n bits comprising one of the P words of data comprising one of the K data blocks, and c) a parity bit output for outputting the series of one bit parity signals generated by the XOR logic device by performing a logical XOR operation on each one of the parity -- block signals in the series of parity -- block signals received by the first signal input, and each corresponding input signal in the series of input signals supplied by the respective line of the bus to the second signal input of the XOR logic device; and iii) a logic block comprising P one bit storage locations arranged in a FIFO data structure for storing the one bit parity signals output by the XOR logic device, the logic block includes a) a first input to receive a FIFO read enable signal, to enable the logic block to output one of P values stored in the logic block's P one bit storage locations as a function of the FIFO read enable signal and the FIFO data structure, b) a second input to receive a FIFO write enable signal, to enable the logic block to store the series of one bit parity signals output by the XOR logic device in one of the logic block's P one bit storage locations as a function of the FIFO write enable signal and the FIFO data structure, c) a parity bit input coupled to the parity bit output of the XOR logic device, and d) a parity -- block signal output coupled to the first input of the XOR logic device and coupled to the one bit parity generator output for outputting the series of one bit parity signals stored in the logic block's P one bit storage locations; and a control logic block for controlling the operation of the parity generator, the control logic block comprising, a) an input coupled to the bus's control and data lines for receiving control and data signals from the bus, b) a FIFO read enable signal output coupled to the first input of each one of the n one bit parity generator circuits'logic blocks, and c) a FIFO write enable signal output coupled to the second input of each one of the n one bit parity generator circuits'logic blocks.

Claim 29

A computer system, comprising: a bus comprising n data lines and a series of control lines; a data storage device coupled to the bus for storing a series of K data blocks, each data block comprising m bits arranged to form P words, each one of the P words comprising a series of n bits; a parity generator coupled to the bus for generating a block of m parity bits from the series of K data blocks, the parity generator comprising a plurality of n one bit parity generator circuits, each parity generator circuit comprising, i) an input and an output being coupled to a respective one of the n data lines of the bus, ii) an XOR logic device including, a) a first input to receive a series of one bit parity -- block signals, b) a second input coupled to the input of the one bit parity generator circuit to receive a series of input signals from the respective data line of the bus each input signal comprising a respective one of the series of n bits comprising one of the P words of data comprising one of the K data blocks, and c) a parity bit output for outputting the series of one bit parity signals generated by the XOR logic device by performing a logical XOR operation on each one of the parity -- block signals in the series of parity -- block signals received by the first signal input, and each corresponding input signal in the series of input signals supplied by the respective line of the bus to the second signal input of the XOR logic device; and iii) a logic block comprising P one bit storage locations arranged in a FIFO data structure for storing the one bit parity signals output by the XOR logic device, the logic block includes a) a first input to receive a FIFO read enable signal, to enable the logic block to output one of P values stored in the logic block's P one bit storage locations as a function of the FIFO read enable signal and the FIFO data structure, b) a second input to receive a FIFO write enable signal, to enable the logic block to store the series of one bit parity signals output by the XOR logic device in one of the logic block's P one bit storage locations as a function of the FIFO write enable signal and the FIFO data structure, c) a parity bit input coupled to the parity bit output of the XOR logic device, and d) a parity -- block signal output coupled to the first input of the XOR logic device and coupled to the one bit parity generator output for outputting the series of one bit parity signals stored in the logic block's P one bit storage locations; and a control logic block for controlling the operation of the parity generator, the control logic block comprising, a) an input coupled to the bus's control and data lines for receiving control and data signals from the bus, b) a FIFO read enable signal output coupled to the first input of each one of the n one bit parity generator circuits'logic blocks, and c) a FIFO write enable signal output coupled to the second input of each one of the n one bit parity generator circuits'logic blocks.