Multiport memory

Claim 2

A multiport memory, comprising: static memory cells; ports provided for writing or reading data to or from said static memory cells; independent bit lines and word lines with levels and corresponding to said ports; switches adapted to electrically connect said bit lines, corresponding to said word lines of a same port, to said static memory cells depending on the levels of said word lines; and short-circuit devices adapted to substantially short-circuit between the bit lines of each column of corresponding ports at a time a same row is selected by the corresponding ports.

Claim 3

A multiport memory according to claim 1, wherein said short circuit devices comprise switches formed of MIS type transistors.

Claim 4

A multiport memory according to claim 2, wherein the switches connected to a same cell are almost a same size.

Claim 5

A multiport memory according to claim 1, wherein said short-circuit devices produce substantial short-circuits between the bit lines of each column of corresponding ports.

Claim 6

A multiport memory, comprising: static memory cells; ports provided for write or read operations to or from said static memory cells; independent bit lines and word lines with signal levels and corresponding to said ports; switches adapted to electrically connect said bit lines, corresponding to said word lines of a same port, to said static memory cells depending on the signal levels of said word lines; and short-circuit devices adapted to substantially short circuit between the bit lines corresponding to the port selected for a write operation among the bit lines corresponding to a plurality of selected ports and other bit lines when word lines belonging to a same row are selected from the plurality of the ports for the write or read operation, said short-circuit devices comprising: a row address matching detection circuit which compares row addresses input to respective ports with each other and outputs a signal when the row addresses of the ports match; and a short-circuit switch connected to said detection circuit and the row bit lines and which receives the output signal from said row address matching detection circuit and short-circuits the bit lines of each column of corresponding ports.

Claim 7

A multiport memory, comprising: static memory cells; ports provided for write or read operations to or from said static memory cells; independent bit lines and word lines with signal levels and corresponding to said ports; switches adapted to electrically connect said bit lines, corresponding to said word lines of a same port, to said static memory cells depending on the signal levels of said word lines; and short-circuit devices adapted to substantially short circuit between the bit lines corresponding to the port selected for a write operation among the bit lines corresponding to a plurality of selected ports and other bit lines when word lines belonging to a same row are selected from the plurality of the ports for the write or read operation, said short-circuit devices comprising: a row address matching detection circuit which compares row addresses input to respective ports with each other and outputs a signal when the row addresses of the ports match; and a short-circuit switch connected to said detection circuit and the row bit lines and which receives the output signal from said row address matching detection circuit and short-circuits the bit lines of each column of corresponding ports.

Claim 8

A multiport memory according to claim 5, wherein said short-circuit switch comprises a MIS type transistor.

Claim 9

A multiport memory according to claim 6, wherein the switches connected to a same one of the cells are formed almost of the same size.

Claim 10

A multiport memory according to claim 5, wherein said short-circuits devices generate short-circuits between the bit lines corresponding to the ports selected for the write operation among the bit lines corresponding to the plurality of the selected ports and other bit lines.

Claim 11

A multiport memory according to claim 5, wherein said short-circuit switch is provided at an end of each bit line located outside of a cell region comprising said static memory cells.

Claim 12

A multiport memory according to claim 5, wherein said short-circuit switch comprises a MIS type transistor.

Claim 13

A multiport memory according to claim 10, wherein a mutual conductance Gm of the MIS type transistor comprising said short-circuit switch is greater than a mutual conductance Gm of a MIS type transistor forming said switches.

Claim 14

A multiport memory, comprising: static memory cells; a first port and a second port provided for a write or a read operation to or from said static memory cells; independent first and second bit lines and independent first and second word lines having levels and provided corresponding to said first and second ports; switches adapted to electrically connect said bit lines corresponding to said first and second word lines of a same port to said static memory cells depending on the levels of said first and second word lines; and short-circuit devices adapted to substantially short circuit between the bit lines of each column of said first and second corresponding ports at a time a same row is selected by said first and second ports.

Claim 15

A multiport memory, comprising: static memory cells; a first port and a second port provided for a write or a read operation to or from said static memory cells; independent first and second bit lines and independent first and second word lines having levels and provided corresponding to said first and second ports; switches adapted to electrically connect said bit lines corresponding to said first and second word lines of a same port to said static memory cells depending on the levels of said first and second word lines; and short-circuit devices adapted to substantially short circuit between the bit lines of each column of said first and second corresponding ports at a time a same row is selected by said first and second ports.

Claim 16

A multiport memory according to claim 12, wherein said short-circuit devices comprise a MIS type transistor.

Claim 17

A multiport memory according to claim 13, wherein the switches which are connected to a same one of the cells are formed almost of a same size.

Claim 18

A multiport memory according to claim 12, wherein said short-circuit devices are provided at an end of each bit line located outside of a cell region comprising said static memory cells.

Claim 19

A multiport memory according to claim 12, wherein said short-circuit devices comprise a short circuit switch comprising a MIS type transistor.

Claim 20

A multiport memory according to claim 16, wherein a mutual conductance Gm of the MIS type transistor comprising said short-circuit switch is greater than to a mutual conductance Gm of a MIS type transistor forming said switches.

Claim 21

A multiport memory, comprising: static memory cells; a first port and a second port provided for a write or a read operation to or from said static memory cells; independent first and second bit lines and independent first and second word lines having levels and provided corresponding to said first and second ports; switches for electrically connecting said bit lines corresponding to said first and second word lines of a same port to said static memory cells depending on cells of said first and second word lines; and short-circuit devices for substantially short-circuiting between the bit lines of each column of corresponding ports at a time a same row is selected by a plurality of said ports, said short-circuit devices comprising: a row address matching detection circuit which compares row addresses input to respective ports with each other and outputs a signal when the row addresses of the plurality of ports match; and a short-circuit switch connected to the detection circuit and to the row bit lines and which receives the signal from said row address matching detection circuit and substantially short circuits the bit lines of each column of corresponding ports.

Claim 22

A multiport memory, comprising: static memory cells; a first port and a second port provided for a write or a read operation to or from said static memory cells; independent first and second bit lines and independent first and second word lines having levels and provided corresponding to said first and second ports; switches for electrically connecting said bit lines corresponding to said first and second word lines of a same port to said static memory cells depending on cells of said first and second word lines; and short-circuit devices for substantially short-circuiting between the bit lines of each column of corresponding ports at a time a same row is selected by a plurality of said ports, said short-circuit devices comprising: a row address matching detection circuit which compares row addresses input to respective ports with each other and outputs a signal when the row addresses of the plurality of ports match; and a short-circuit switch connected to the detection circuit and to the row bit lines and which receives the signal from said row address matching detection circuit and substantially short circuits the bit lines of each column of corresponding ports.

Claim 23

A multiport memory according to claim 18, wherein said short circuit switch comprises a MIS type transistor.

Claim 24

A multiport memory according to claim 18, wherein the switches connected to a same a same one of said cells are formed almost of a same size.

Claim 25

A multiport memory according to claim 20, wherein said short-circuit switch is provided at an end of each bit line located outside of a cell region comprising said static memory cells.

Claim 26

A multiport memory according to claim 21, wherein said short-circuit switch comprises a MIS type transistor.

Claim 27

A multiport memory according to claim 22, wherein a mutual conductance Gm of the MIS type transistor forming said short-circuit switch is greater than a mutual conductance Gm of a MIS type transistor forming said switches.

Claim 28

A multiport memory, comprising: static memory cells; a first port and a second port provided for a write or a read operation to or from said static memory cells; first and second bit lines and first and second word lines having levels and provided corresponding to said first and second ports; switches for electrically connecting said bit lines corresponding to said first and second word lines of a same port to said static memory cells depending on the levels of said first and second word lines; and short-circuit devices for substantially short-circuiting the bit lines corresponding to the ports selected for the write operation and other selected bit lines among the first and second bit lines, when the first and second word lines belonging to a same row are selected from the read or the write operation; a row address matching detection circuit which compares row addresses input to respective ports with each other and outputs a signal when the row addresses of the ports including those selected for the write operation match; a first cell region and a second cell region which may be formed by dividing said word lines in a cell region of said static memory cells into two regions; a right row decoder provided between said first cell region and said second cell region, corresponding to a right port; and a left row decoder provided between said first cell region and said second cell region, corresponding to a left port; and said short-circuit devices receive an output of said row address matching detection circuit and generate a short-circuit of the bit lines corresponding to the ports selected for the write operation and other selected bit lines, among the bit lines corresponding to the respective ports.

Claim 29

A multiport memory, comprising: static memory cells; a first port and a second port provided for a write or a read operation to or from said static memory cells; first and second bit lines and first and second word lines having levels and provided corresponding to said first and second ports; switches for electrically connecting said bit lines corresponding to said first and second word lines of a same port to said static memory cells depending on the levels of said first and second word lines; and short-circuit devices for substantially short-circuiting the bit lines corresponding to the ports selected for the write operation and other selected bit lines among the first and second bit lines, when the first and second word lines belonging to a same row are selected from the read or the write operation; a row address matching detection circuit which compares row addresses input to respective ports with each other and outputs a signal when the row addresses of the ports including those selected for the write operation match; a first cell region and a second cell region which may be formed by dividing said word lines in a cell region of said static memory cells into two regions; a right row decoder provided between said first cell region and said second cell region, corresponding to a right port; and a left row decoder provided between said first cell region and said second cell region, corresponding to a left port; and said short-circuit devices receive an output of said row address matching detection circuit and generate a short-circuit of the bit lines corresponding to the ports selected for the write operation and other selected bit lines, among the bit lines corresponding to the respective ports.

Claim 30

A multiport memory according to claim 24, wherein said switching devices comprise a MIS type transistor.

Claim 31

A multiport memory according to claim 24, wherein the switches corresponding to a same port and belonging to a same column are formed almost of a same size.

Claim 32

A multiport memory according to claim 26 further comprising: a data bus line provided corresponding to each port; a column selecting transistor formed to enable electrical connection of said cells with said bit lines corresponding to the same port to which said data bus line also corresponds; a first load circuit formed to enable said bit lines to be maintained at a predetermined voltage; and a second load circuit formed to enable said data bus line to be maintained at the predetermined voltage.

Claim 33

A multiport memory according to claim 26, wherein said short-circuit devices comprise a short-circuit switch at an end of each bit line located outside of a cell region comprising said static memory cells.

Claim 34

A multiport memory according to claim 26, wherein said short-circuit switch comprises a MIS type transistor.

Claim 35

A multiport memory according to claim 29, wherein a mutual conductance gm of the MIS type transistor forming said short-circuit switch is greater than a mutual conductance of a MIS type transistor forming an said switches.

Claim 36

A multiport memory according to claim 1, further comprising: data bus lines provided corresponding to each port; a column selected transistor formed to enable electrical connection between said bit lines corresponding to the same port to which said data bus also corresponds; a first load circuit formed to enable said bit line to be maintained at a predetermined voltage; and a second load circuit formed to enable said data bus line to be maintained at the predetermined voltage.

Claim 37

A multiport memory, comprising: static memory cells arranged in an array of rows and columns and having at least two independent bit lines corresponding to at least two ports providing cell addresses; and a short circuit device coupled to the independent bit lines and to receive the cell addresses and short circuit connecting between the bit lines of corresponding columns at a time that the cell addresses match.

Claim 38

A multiport memory, comprising: static memory cells arranged in an array of rows and columns and having at least two independent bit lines corresponding to at least two ports providing cell addresses; and a short circuit device coupled to the independent bit lines and to receive the cell addresses and short circuit connecting between the bit lines of corresponding columns at a time that the cell addresses match.

Claim 39

A memory as recited in claim 31, wherein said short circuit device comprises: a row address matching circuit adapted to receive the cell addresses; and a short circuit transistor connected to said row address matching circuit and between one of the two bit lines and one of the other bit lines.