Imaging system with multilevel dithering using bit shifter

Claim 3

The apparatus as in claim 1, wherein the dither template values are normalized by symmetrically distributing the dither template values between 0 and the average number of unique S values.

Claim 4

The apparatus as in claim 2, wherein the normalized dither template values (D<x',y'>) are related to a number of input levels (NIL); a number of output levels (NOL); a Δ Q ; a Δ d ; a dither template (T<x',y'>); and a number of template levels of the imaging system (NTL) by: Δ.sub.Q =(NIL-1)/(NOL-1); Δ.sub.d =Δ.sub.Q /(NTL); and D<x',y'>=int {Δ.sub.d (T<x',y'>)+0.5}.

Claim 5

The apparatus as in claim 3, wherein the dither template values are phase adjusted by spatially shifting the values within the dither template.

Claim 6

The apparatus as in claim 4, wherein the phase adjusted dither template values (d<x',y'>) are related to a number of input levels (NIL); a number of output levels (NOL); a Δ Q ; a Δ d ; a dither template (T<x',y'>); a number of template levels of the imaging system (NTL); a phase value of the x,y address of an input cell (phase -- x, phase -- y); and the dimensions of said memory means (M mm , N mm ) by: Δ.sub.Q =(NIL-1)/(NOL-1); Δ.sub.d =Δ.sub.Q /(NTL); D<x',y'>=int {Δ.sub.d (T<x',y'>)+0.5}; and d<x',y'>=D<(x'+phase.sub.-- x)modulo(M.sub.mm), (y'+phase.sub.- y)modulo(N.sub.mm)>.

Claim 7

The apparatus as in claim 1, wherein said shifter means shifts the S value R bits to the right, where R=int{log.sub.2 (2.sup.B -1)/(NOL-1)}; B=the number of bits of the input level; and NOL=the number of output levels.

Claim 10

The apparatus as in claim 7, wherein the dither template values are normalized by symmetrically distributing the dither template values between 0 and the average number of unique S values.

Claim 11

The apparatus as in claim 8, wherein the dither template values are phase adjusted by spatially shifting the values within the dither template.

Claim 12

An apparatus as in claim 9, further comprising an image adjustment system, said image adjustment system being responsive to a raw input level produced by an input device to provide an input level to said adding means.

Claim 13

The apparatus as in claim 7, wherein said shifter means shifts the S value R bits to the right, where R=int {log.sub.2 (2.sup.B -1)/(NOL-1)}; B=the number of bits of the input level; and NOL=the number of output levels.

Claim 14

An imaging system comprising: an input device for producing input levels; an output device for producing output levels; an image processor, coupled between said input and output devices, for translating the input levels to corresponding output levels, said image processor including: Look Up Table (LUT) generator means for generating dither template value for the input levels of an imaging system; memory means for storing the dither template values generated by the LUT generator means, said memory means being responsive to an address of an input cell of an input device to provide a dither template value which corresponds to the address of the input cell; means for adding an input level of the input cell to the dither template value provided by said memory means to provide a sum (S), said adding means producing a finite number of unique S values which map to a single, given output levels; shifter means for bit shifting the S value provided by the adding means; and both the number of input levels and the number of output levels produced by the imaging system being any number, provided the number of input levels is equal to or greater than the number of output levels, and further provided that an average number of unique S values, determined by averaging the number of unique S values which map to each of the given output levels, is equal to an integer power of two.

Claim 15

An imaging system comprising: an input device for producing input levels; an output device for producing output levels; an image processor, coupled between said input and output devices, for translating the input levels to corresponding output levels, said image processor including: Look Up Table (LUT) generator means for generating dither template value for the input levels of an imaging system; memory means for storing the dither template values generated by the LUT generator means, said memory means being responsive to an address of an input cell of an input device to provide a dither template value which corresponds to the address of the input cell; means for adding an input level of the input cell to the dither template value provided by said memory means to provide a sum (S), said adding means producing a finite number of unique S values which map to a single, given output levels; shifter means for bit shifting the S value provided by the adding means; and both the number of input levels and the number of output levels produced by the imaging system being any number, provided the number of input levels is equal to or greater than the number of output levels, and further provided that an average number of unique S values, determined by averaging the number of unique S values which map to each of the given output levels, is equal to an integer power of two.

Claim 16

The imaging system as in claim 12, wherein the dither template values are normalized by symmetrically distributing the dither template values between 0 and the average number of unique S values.

Claim 17

The imaging system as in claim 13, wherein the dither template values are phase adjusted by spatially shifting the values within the dither template.

Claim 18

The imaging system as in claim 12, further comprising a second image processor, and wherein the input levels of the input device are components of a color system.

Claim 21

The method as in claim 16, wherein said generating step includes: normalizing the dither template values by distributing the dither template values between 0 and the average number of unique S values.

Claim 22

The method as in claim 17, wherein said generating step includes: phase adjusting the dither template values by spatially shifting the values within the dither template.

Claim 23

The method as in claim 16, wherein said shifting step includes shifting the S value R bits to the right, where R=int{log.sub.2 (2.sup.B -1)/(NOL-1)}; B=the number of bits of the input level; and NOL=the number of output levels.