Inverter power source

Claim 2

An inverter power supply for driving an electrical device comprising: a DC supply providing a DC voltage; a transformer having a primary winding, a secondary winding, and a feedback winding; a self-excited oscillator comprising a FET transistor which is connected in series with said primary winding across said DC supply and energized by said DC supply to generate a high frequency voltage across said primary winding, a high frequency feedback voltage across said feedback winding and a resulting output AC voltage across said secondary winding, said output AC voltage being applied to a load circuit of said device; a biasing capacitor connected in series with said feedback winding across a gate-source path of said FET transistor for providing an offset voltage which is additive to said high frequency feedback voltage developed across said feedback winding to give a bias voltage applied to a gate of said FET transistor so as to alternately turn on and off said FET transistor for driving said self-excited oscillator; bias stabilizing circuit which lowers said offset voltage by discharging said biasing capacitor through said FET transistor being turned on, thereby driving said FET transistor turned on only for substantially a constant ON-time period irrespective of an increase in said DC voltage within a limited range; and bias compensation means comprising an auxiliary feedback winding coupled to said primary winding and connected in parallel with said biasing capacitor to induce a voltage of opposite polarity to said feedback voltage induced at said feedback winding, said bias compensation means producing a negative voltage and superimposing said negative voltage to said offset voltage, thereby permitting said offset voltage to be lowered to negative so as to correspondingly lower the bias voltage when said DC voltage increases over said limited range.

Claim 3

An inverter power supply as set forth in claim 1, wherein said oscillator includes a capacitor connected in parallel with said primary winding to form therewith a parallel resonance circuit for providing said high frequency voltage by resonance.

Claim 4

An inverter power supply as set forth in claim 1, wherein said bias stabilizing circuit comprises a bypass diode and a resistor connected in series between a drain terminal of said FET transistor and a first end of said feedback winding, said feedback winding having a second end connected to a gate terminal of said FET transistor, and wherein said bias compensation means further comprises a smoothing capacitor being connected in series with a diode across said auxiliary feedback winding for smoothing said voltage induced at said auxiliary feedback winding and superimposing a resulting smoothed voltage to said offset voltage as said negative voltage when said FET transistor is turned on.

Claim 5

An inverter power supply for driving an electrical device comprising: a DC supply providing a DC voltage; a transformer having a primary winding, a secondary winding, and a feedback winding; a self-excited oscillator comprising an FET transistor which is connected in series with said primary winding across said DC supply and energized by said DC supply to generate a high frequency voltage across said primary winding, a high frequency feedback voltage across said feedback winding and a resulting output AC voltage across said secondary winding, said output AC voltage being applied to a load circuit of said device; a biasing capacitor connected in series with said feedback winding across a gate-source path of said FET transistor for providing an offset voltage which is additive to said high frequency feedback voltage developed across said feedback winding to give a bias voltage applied to a gate terminal of said FET transistor so as to alternately turn on and off said FET transistor for driving said self-excited oscillator; bias stabilizing circuit which lowers said offset voltage by discharging said biasing capacitor through said FET transistor being turned on, said bias stabilizing circuit comprising a bypass diode and a resistor connected in series between a drain terminal of said FET transistor and a first end of said feedback winding, said feedback winding having a second end connected to the gate terminal of said FET transistor; a blocking diode connected in series between said drain terminal of said FET transistor and said bias stabilizing circuit in an opposite direction with respect to a parasitic diode of said FET transistor such that a current due to a negative going voltage developed at said primary winding is blocked from flowing through said DC source and through said parasitic diode, thereby permitting a voltage at said drain terminal of said FET to be lowered negative in response to said negative going voltage and therefore permitting said biasing capacitor to discharge through said bypass diode, said blocking diode, and said FET transistor for lowering said offset voltage to negative.

Claim 6

An inverter power supply for driving an electrical device comprising: a DC supply providing a DC voltage; a transformer having a primary winding, a secondary winding, and a feedback winding; a self-excited oscillator comprising an FET transistor which is connected in series with said primary winding across said DC supply and energized by said DC supply to generate a high frequency voltage across said primary winding, a high frequency feedback voltage across said feedback winding and a resulting output AC voltage across said secondary winding, said output AC voltage being applied to a load circuit of said device; a biasing capacitor connected in series with said feedback winding across a gate-source path of said FET transistor for providing an offset voltage which is additive to said high frequency feedback voltage developed across said feedback winding to give a bias voltage applied to a gate terminal of said FET transistor so as to alternately turn on and off said FET transistor for driving said self-excited oscillator; bias stabilizing circuit which lowers said offset voltage by discharging said biasing capacitor through said FET transistor being turned on, said bias stabilizing circuit comprising a bypass diode and a resistor connected in series between a drain terminal of said FET transistor and a first end of said feedback winding, said feedback winding having a second end connected to the gate terminal of said FET transistor; a blocking diode connected in series between said drain terminal of said FET transistor and said bias stabilizing circuit in an opposite direction with respect to a parasitic diode of said FET transistor such that a current due to a negative going voltage developed at said primary winding is blocked from flowing through said DC source and through said parasitic diode, thereby permitting a voltage at said drain terminal of said FET to be lowered negative in response to said negative going voltage and therefore permitting said biasing capacitor to discharge through said bypass diode, said blocking diode, and said FET transistor for lowering said offset voltage to negative.

Claim 7

An inverter power supply as set forth in claim 4, wherein said oscillator includes a capacitor connected in parallel with said primary winding to form therewith a parallel resonance circuit for providing said high frequency voltage by resonance.

Claim 8

An inverter power supply as set forth in claim 4, further including a return resistor connected in parallel with said blocking diode for discharging a parasitic capacitor of said FET transistor through said return resistor to said oscillator when said FET transistor is turned off.

Claim 9

An inverter power supply as set forth in claim 4, further including a voltage dividing resistor connected between a source terminal of said FET transistor and said biasing capacitor so as to increase a threshold voltage of said FET transistor in proportion to a current flowing through said voltage dividing resistor when said FET transistor is turned on.

Claim 10

An inverter power supply as set forth in claim 4, further including limit switch means which is connected in a gate-source path of said FET transistor so as to shunt the gate-source path when said FET transistor sees a current exceeding a predetermined level.

Claim 11

An inverter power supply as set forth in claim 8, wherein said limit switch means comprises a bipolar transistor connected in said gate-source path of said FET transistor and a current sensing resistor connected between said source terminal of said FET transistor and an emitter terminal of said bipolar transistor, said bipolar transistor having a gate terminal connected to a point between said current sensing resistor and the source terminal of said FET so as to become conductive when said current sensing resistor sees a current exceeding said predetermined level and shunt said gate-source path of said FET to turn it off