Apparatus and method for reading, writing, and refreshing memory with direct virtual or physical access

Claim 2

A computer memory system capable of receiving a plurality of virtual or physical address requests, comprising: a row and column-addressable random access memory having at least one row address latch capable of indicating a plurality of memory locations, all of said indicated memory locations having a common physical row address; at least a first register for storing at least portions of a row address corresponding to said common physical row address during at least a first and a second of said plurality of address requests, wherein the contents of said first register comprises at least portions of a virtual address during a first time period and at least portions of a physical address, different from said virtual address, during a second time period said second time period being different from said first time period; and a comparator for receiving at least portions of an address request and for comparing said at least portions of an address request to at least portions of said first register to determine whether the memory location indicated by said address request is included in said plurality of memory locations wherein said at least portions of an address request comprises at least portions of one of said plurality of virtual or physical address requests and wherein said comparitor is used to compare said at least portions of an address request to said at least portions of said first register when said one of said plurality of virtual or physical address requests is a virtual address request and wherein said comparitor is also used to compare said at least portions of an address request to said at least portions of said first register when said one of said plurality of virtual or physical address requests is a physical address request.

Claim 3

A memory system, as claimed in claim 1, further comprising at least a second storage register for storing at least portions of said common physical row address.

Claim 4

A memory system, as claimed in claim 1, wherein said random access memory has a plurality of row address latches and wherein each of said plurality of row address latches is associated with a register for storing a row address selected from the group consisting of a physical address and a virtual address.

Claim 5

A memory system, as claimed in claim 1, wherein said memory system includes at least two functional units, and wherein at least one functional unit comprises means for determining whether the requested address resides on said one functional unit.

Claim 6

A computer memory system as claimed in claim 1, further comprising: means for distinguishing between said virtual and physical address requests; and means for setting a first digital bit to indicate whether said first address request is virtual or physical.

Claim 7

A computer memory system, as claimed in claim 5, further comprising: means for setting a second digital bit to indicate whether said second address request is virtual or physical; and a comparator for comparing said second digital bit with said first digital bit.

Claim 8

A memory system, as claimed in claim 5, wherein said means for storing said first digital bit comprises a register, and further comprising means for storing in said register at least portions of the address for said first address request, wherein said address is selected from the group consisting of a physical address and a virtual address.

Claim 9

A memory system for accessing memory elements in an array having a first plurality of memory elements in response to a sequential plurality of memory address requests, at least one of said memory address requests having a correspondence with at least one of said first plurality of memory elements, comprising: an array of memory elements, each element having an address comprising a first number of row address bits and a second number of column address bits; first address register means for holding a third number of column address bits for use in accessing a memory element having an address which includes said third number of column bits, said third number being less than said second number; second means, using a fourth number of column address bits, for use in accessing a memory element having an address which includes said fourth number of column address bits, said fourth number being less than said second number; third means for providing a number of bits from each of said sequential plurality of memory address requests to said first address register, said provided number being equal to said third number; fourth means for continuously maintaining said fourth number of column bits in said second means during at least two of said sequential plurality of memory address requests; and fifth means for accessing at least one of said first plurality of memory elements using said third number of column address bits in said first address register means, and said fourth number of column address bits in said second means.

Claim 10

A memory system for accessing memory elements in an array having a first plurality of memory elements in response to a sequential plurality of memory address requests, at least one of said memory address requests having a correspondence with at least one of said first plurality of memory elements, comprising: an array of memory elements, each element having an address comprising a first number of row address bits and a second number of column address bits; first address register means for holding a third number of column address bits for use in accessing a memory element having an address which includes said third number of column bits, said third number being less than said second number; second means, using a fourth number of column address bits, for use in accessing a memory element having an address which includes said fourth number of column address bits, said fourth number being less than said second number; third means for providing a number of bits from each of said sequential plurality of memory address requests to said first address register, said provided number being equal to said third number; fourth means for continuously maintaining said fourth number of column bits in said second means during at least two of said sequential plurality of memory address requests; and fifth means for accessing at least one of said first plurality of memory elements using said third number of column address bits in said first address register means, and said fourth number of column address bits in said second means.

Claim 11

A memory system, as claimed in claim 8, wherein said array of memory elements further comprises at least a first row address latch capable of indicating a second plurality of memory elements, said second plurality of memory elements including at least some of said first plurality of memory elements, wherein said first row address latch continuously indicates said second plurality of memory elements at least until a first condition occurs, said first condition occurring at least when one of said plurality of memory address requests has no correspondence with said second plurality of memory elements; and said means for maintaining comprises means for maintaining said fourth number of column bits in said second means until at least said first condition occurs.

Claim 12

A memory system, as claimed in claim 8, wherein the difference between said second number and said fourth number is 8.

Claim 13

A memory system, as claimed in claim 8, wherein said second number equals said third number plus said fourth number.

Claim 14

A memory system, as claimed in claim 8, wherein said first number equals 10, said second number equals 10, and said fourth number equals 2.

Claim 15

A memory system, as claimed in claim 8, wherein said fourth number is greater than 2.

Claim 16

A computer memory system comprising: a fast page random access column- and row-organized memory, including first, second, third, and fourth address latches, each row latch for holding an address indicating one row of said memory so that the contents of memory in said row can be rapidly accessed by strobing a CAS signal, said row being specifiable by a row address, each element in said memory array having an address comprising at least 10 row address bits and at least 10 column address bits; a first address register for holding at least eight column address bits usable in accessing a memory element in a row indicated by one of said row address latches; a first means for holding at least two column address bits usable in accessing a memory element in at least one of said row address latches; a memory request register for holding bits comprising the requested addresses of a sequential plurality of requested memory elements, wherein said requested addresses are selected from the group consisting of physical addresses and virtual addresses; means for providing eight column address bits from each of said sequential plurality of memory address requests in said memory request register to said first address register; first, second, third, and fourth virtual/physical row address registers for holding a row address corresponding to the row held by said first, second, third, and fourth row address latches, respectively, said row address selected from the group consisting of a physical address and a virtual address; first, second, third, and fourth physical address registers, each physical address register holding a physical row address corresponding to the row indicated by said first, second, third, and fourth row address latches, respectively, and also holding at least two column address bits corresponding to a column address usable in accessing a memory element having a column address which includes said two column address bits; a comparator for comparing at least a first plurality of bits from an address in said memory request register to the contents of each of said first, second, third, and fourth virtual/physical address registers, and for generating a first signal when the contents of at least one of said first, second, third, or fourth virtual/physical address registers is identical to said first plurality of bits, and for generating a second signal when the contents of none of said first, second, third, or fourth virtual/physical address registers are identical to said first plurality of bits; third means for continuously maintaining said two column bits in said first means during at least two of said plurality of memory address requests, until said second signal is generated; fourth means for changing the contents of at least one of said first, second, third or fourth row address latches following generation of said second signal; and fifth means for determining whether said memory request address is a virtual address or a physical address, and for setting at least one bit in said memory request register to indicate whether said memory request address is a virtual address or a physical address.

Claim 17

A computer memory system comprising: a fast page random access column- and row-organized memory, including first, second, third, and fourth address latches, each row latch for holding an address indicating one row of said memory so that the contents of memory in said row can be rapidly accessed by strobing a CAS signal, said row being specifiable by a row address, each element in said memory array having an address comprising at least 10 row address bits and at least 10 column address bits; a first address register for holding at least eight column address bits usable in accessing a memory element in a row indicated by one of said row address latches; a first means for holding at least two column address bits usable in accessing a memory element in at least one of said row address latches; a memory request register for holding bits comprising the requested addresses of a sequential plurality of requested memory elements, wherein said requested addresses are selected from the group consisting of physical addresses and virtual addresses; means for providing eight column address bits from each of said sequential plurality of memory address requests in said memory request register to said first address register; first, second, third, and fourth virtual/physical row address registers for holding a row address corresponding to the row held by said first, second, third, and fourth row address latches, respectively, said row address selected from the group consisting of a physical address and a virtual address; first, second, third, and fourth physical address registers, each physical address register holding a physical row address corresponding to the row indicated by said first, second, third, and fourth row address latches, respectively, and also holding at least two column address bits corresponding to a column address usable in accessing a memory element having a column address which includes said two column address bits; a comparator for comparing at least a first plurality of bits from an address in said memory request register to the contents of each of said first, second, third, and fourth virtual/physical address registers, and for generating a first signal when the contents of at least one of said first, second, third, or fourth virtual/physical address registers is identical to said first plurality of bits, and for generating a second signal when the contents of none of said first, second, third, or fourth virtual/physical address registers are identical to said first plurality of bits; third means for continuously maintaining said two column bits in said first means during at least two of said plurality of memory address requests, until said second signal is generated; fourth means for changing the contents of at least one of said first, second, third or fourth row address latches following generation of said second signal; and fifth means for determining whether said memory request address is a virtual address or a physical address, and for setting at least one bit in said memory request register to indicate whether said memory request address is a virtual address or a physical address.

Claim 18

Apparatus for translating at least one of a plurality of virtual addresses to a corresponding physical address, comprising: a first table having a plurality of entries, each entry containing data for translating a virtual address to a physical address; a second table containing a plurality of entries; means for making a corresponding change to said second table whenever there is a change made to said first table, wherein said second table is substantially identical to said first table; means for detecting an error condition in said first table; means for translating a virtual address to a physical address using only said first table, and without using said second table, during a period when no errors have been detected by said means for detecting an error; and means for selecting said second table for use by said means for translating and for discontinuing use of said first table when an error condition is detected by said means for detecting.

Claim 19

Apparatus for translating at least one of a plurality of virtual addresses to a corresponding physical address, comprising: a first table having a plurality of entries, each entry containing data for translating a virtual address to a physical address; a second table containing a plurality of entries; means for making a corresponding change to said second table whenever there is a change made to said first table, wherein said second table is substantially identical to said first table; means for detecting an error condition in said first table; means for translating a virtual address to a physical address using only said first table, and without using said second table, during a period when no errors have been detected by said means for detecting an error; and means for selecting said second table for use by said means for translating and for discontinuing use of said first table when an error condition is detected by said means for detecting.

Claim 20

A computer memory system as claimed in claim 1, further comprising: a plurality of memory functional units, each functional unit for storing a plurality of pages of memory; a page table cache comprising a plurality of page table cache entry arrays and at least a first page table cache tag array, each of said page table cache entry arrays associated with one of said memory functional units for storing physical addresses residing on said functional unit, said page table cache tag array for storing indications of virtual addresses, each virtual address indication corresponding to a physical address stored in a page table entry array, wherein said first page table cache tag array includes at least a first indication of a virtual address corresponding to a physical address stored in a first of said plurality of page table entry arrays and a second indication of a virtual address corresponding to a physical address stored in a second of said plurality of page table entry arrays.

Claim 21

A memory system, as claimed in claim 16, wherein said first page table cache tag array stores indications of virtual addresses for memory locations containing data, and further comprising a second page table cache tag array for storing indications of virtual addresses for memory locations containing instructions.

Claim 24

A method, as claimed in claim 18, wherein: said step of providing a memory array comprises providing a plurality of row address latches; said step of providing virtual/physical address registers comprises providing one virtual/physical address register for each row address latch; said step of comparing comprises comparing said selected bits to the contents of each of said plurality of virtual/physical registers, and generating a third signal when no contents of said virtual/physical registers are equal to said selected bits; and further comprising changing the contents of at least a first row address latch in response to said third signal.

Claim 27

A computer memory system, as claimed in claim 1, further comprising:

Claim 28

A method, as claimed in claim 20, further comprising: determining whether each of said sequential plurality of memory address requests is virtual or physical; setting at least a first bit to indicate whether each of said memory address request is virtual or physical; wherein said step of accessing a memory element includes using said set bit indicating whether said memory address request is virtual or physical. a first table having a plurality of entries, each entry containing data for translating a virtual address to a physical address; a second table containing a plurality of entries; means for making a corresponding change to said second table whenever there is a change made to said first table, wherein said second table is substantially identical to said first table; means for detecting an error condition in said first table; means for selectably using one of said first table and second table to translate a virtual address to a physical address; and means for selecting said second table for use by said means for selectably using when an error condition is detected by said means for detecting.