Clock recovery stabilization method and circuit in a receiver of a code division multiple access/direct sequence (CDMA/DS) system

Claim 2

A process for down-converting a spread spectrum signal with first and second local oscillating signals, generating an amplified signal by amplifying the down-converted signal, separating the amplified signal into intermediate base band signals for I and Q channels, and demodulating the separated signals in a code division multiple access/direct sequence receiver, wherein said step of separating the amplified signal into intermediate base band signals for I and Q channels comprises the steps of: squaring said amplified signal to provide a square wave signal, producing a filtered signal by filtering said square wave signal, said filtered signal being a spread spectrum signal of N times an intermediate frequency, and limit-amplifying the filtered signal to provide a limited signal maintained at a given amplitude; generating an adjusted signal by automatically adjusting an input amplitude of said limited signal to exhibit a deviation of less than one decibel; dividing a frequency of said automatically adjusted signal by N to produce an intermediate frequency signal; recovering a clock signal by making a comparison of said intermediate frequency signal with a feedback signal, producing an oscillation signal in response to a phase difference obtained by said comparison, and limit-amplifying said oscillation signal to recover said clock signal; maintaining said oscillating signal at a constant amplitude; dividing a frequency of said oscillation signal by N to produce said feedback signal; and dividing said frequency of said oscillation signal to produce a stable carrier signal, phase shifting said stable carrier signal, in quadrature, to produce first and second carrier signals and separately mixing said amplified signal with the first and second carrier signals to provide said intermediate base band signals for said I and Q channels.

Claim 3

A circuit for a receiver of a code division multiple access/direct sequence system, wherein a received spread spectrum signal is down-converted by first and second local oscillation signals, the down-converted signal is amplified, the amplified signal is separated into intermediate base band signals for I and Q channels in first and second mixers in response with the output of a phase shifter, and the separated signals are demodulated in a synchronous demodulator, said circuit comprising: first means for squaring said amplified signal to produce a square wave signal, producing a filtered signal by filtering said square wave signal, said filtered signal having a frequency of N times an intermediate frequency, and limit-amplifying the filtered signal to produce a limited signal maintained at a given amplitude; second means for generating an adjusted signal by automatically adjusting an input amplitude of said limited signal to a deviation less than a select valve; third means for recovering a clock signal by dividing said adjusted signal to produce an intermediate frequency signal, producing a feedback by amplifying and dividing said intermediate signal, comparing said intermediate frequency signal with said feedback signal to produce a phase difference signal, producing an oscillation signal in response to said phase difference signal, and limit-amplifying said oscillation signal to recover said clock signal; and fourth means for providing a carrier signal by maintaining constant an output amplitude of the clock signal, said carrier signal being provided to said phase shifter for phase shifting said stable carrier signal, in quadrature, to produce first and second carrier signals and supplying the first and second carrier signals to said first and second mixers, wherein said amplified signal provided to said first and second mixers is divided into said intermediate base band signals.

Claim 4

A circuit for a receiver of a code division multiple access/direct sequence system, wherein a received spread spectrum signal is down-converted by first and second local oscillation signals, the down-converted signal is amplified, the amplified signal is separated into intermediate base band signals for I and Q channels in first and second mixers in response with the output of a phase shifter, and the separated signals are demodulated in a synchronous demodulator, said circuit comprising: first means for squaring said amplified signal to produce a square wave signal, producing a filtered signal by filtering said square wave signal, said filtered signal having a frequency of N times an intermediate frequency, and limit-amplifying the filtered signal to produce a limited signal maintained at a given amplitude; second means for generating an adjusted signal by automatically adjusting an input amplitude of said limited signal to a deviation less than a select valve; third means for recovering a clock signal by dividing said adjusted signal to produce an intermediate frequency signal, producing a feedback by amplifying and dividing said intermediate signal, comparing said intermediate frequency signal with said feedback signal to produce a phase difference signal, producing an oscillation signal in response to said phase difference signal, and limit-amplifying said oscillation signal to recover said clock signal; and fourth means for providing a carrier signal by maintaining constant an output amplitude of the clock signal, said carrier signal being provided to said phase shifter for phase shifting said stable carrier signal, in quadrature, to produce first and second carrier signals and supplying the first and second carrier signals to said first and second mixers, wherein said amplified signal provided to said first and second mixers is divided into said intermediate base band signals.

Claim 5

The circuit as claimed in claim 2, wherein said first means comprises a squaring circuit for receiving said amplified signal, a band pass filter for filtering said square wave signal and a limiting amplifier for limit-amplifying said filtered signal to said given amplitude.

Claim 6

The circuit as claimed in claim 2, wherein said second means comprises an automatic level control circuit for receiving said limited signal.

Claim 7

The circuit as claimed in claim 2, wherein said third means comprises: first dividing means for receiving said automatically adjusted signal and for dividing by N to produce said intermediate frequency signal; first amplifying means for receiving and amplifying said clock signal; second dividing means for receiving and/or dividing the amplified clock signal to produce said feedback signal; phase detection means for producing said phase difference signal; means for filtering said phase difference signal; voltage controlled oscillation means for producing said oscillation signal in response to the filtered phase difference signal; and second amplifying means for limiting-amplifying said oscillation signal to provide said clock signal.

Claim 8

The circuit as claimed in claim 2, wherein said fourth means comprises: means for dividing said clock signal to produce a divided clock signal; means for filtering said divided clock signal; and means for amplifying the filtered divided clock signal for producing said stable carrier signal.

Claim 9

A circuit for a receiver of a code division multiple access/direct sequence system, said circuit comprising: down conversion means for down converting a received spread spectrum signal and for generating a down-converted signal; first amplifier means for amplifying and power dividing said down-converted signal and for generating a first amplified signal; a squaring circuit for squaring said first amplified signal and for generating a squared signal; first filter means for filtering said squared signal; first limiting-amplifying means for receiving the filtered squared signal and for generating a limited signal maintained at a given level; automatic adjusting means for automatically adjusting an input level of said limited signal to have a deviation under a selected valve to produce an automatically adjusted signal having a supplemented input dynamic range; first divider means for dividing said limited signal by N to produce an intermediate frequency signal; a phase detector for comparing said intermediate frequency signal to a feedback signal and for producing a phase difference signal; first means for filtering said phase difference signal, generating an oscillation signal in response to the filtered difference signal and limiting-amplifying the oscillation signal to produce a recovered clock signal; second amplifier means for amplifying said recovered clock signal; second divider means for dividing the amplified recovered clock signal to produce said feedback signal; second means for generating a divided clock signal by dividing said recovered clock signal, filtering the divided clock signal and amplifying the filtered divided clock signal to generate a stable carrier signal; third means for receiving said stable carrier signal and for producing a first carrier signal and a second carrier signal shifted in phase from said first carrier signal; fourth means for receiving and separating said first amplified signal into first and second intermediated base band signals in response to said first and second carrier signals, respectively; and fifth means for synchronously demodulating said first and second intermediate base band signals.

Claim 10

A circuit for a receiver of a code division multiple access/direct sequence system, said circuit comprising: down conversion means for down converting a received spread spectrum signal and for generating a down-converted signal; first amplifier means for amplifying and power dividing said down-converted signal and for generating a first amplified signal; a squaring circuit for squaring said first amplified signal and for generating a squared signal; first filter means for filtering said squared signal; first limiting-amplifying means for receiving the filtered squared signal and for generating a limited signal maintained at a given level; automatic adjusting means for automatically adjusting an input level of said limited signal to have a deviation under a selected valve to produce an automatically adjusted signal having a supplemented input dynamic range; first divider means for dividing said limited signal by N to produce an intermediate frequency signal; a phase detector for comparing said intermediate frequency signal to a feedback signal and for producing a phase difference signal; first means for filtering said phase difference signal, generating an oscillation signal in response to the filtered difference signal and limiting-amplifying the oscillation signal to produce a recovered clock signal; second amplifier means for amplifying said recovered clock signal; second divider means for dividing the amplified recovered clock signal to produce said feedback signal; second means for generating a divided clock signal by dividing said recovered clock signal, filtering the divided clock signal and amplifying the filtered divided clock signal to generate a stable carrier signal; third means for receiving said stable carrier signal and for producing a first carrier signal and a second carrier signal shifted in phase from said first carrier signal; fourth means for receiving and separating said first amplified signal into first and second intermediated base band signals in response to said first and second carrier signals, respectively; and fifth means for synchronously demodulating said first and second intermediate base band signals.

Claim 11

The circuit as claimed in claim 7, wherein said down conversion means comprises first and second mixers responsive to first and second local oscillation signals, respectively.

Claim 12

The circuit as claimed in claim 7, wherein said first filter means comprises a band pass filter, and said first limiting-amplifying means comprises a limiting amplifier.

Claim 13

The circuit as claimed in claim 7, wherein said automatic adjusting means comprises an automatic level control circuit.

Claim 14

The circuit as claimed in claim 7, wherein said first divider means comprises a divider and N is equal to 2.

Claim 15

The circuit as claimed in claim 7, wherein said first means comprises: means for filtering said phase difference signal; means for generating said oscillation signal in response to the filtered difference signal; and means for producing said recovered clock signal in response to said oscillation signal.

Claim 16

The circuit as claimed in claim 7, wherein said second means comprises: means for dividing said recovered clock signal by two to provide a divided signal; means for filtering said divided signal; and means for amplifying the filtered signal to generate the stable carrier signal.

Claim 17

The circuit as claimed in claim 7, wherein said third means comprises means for phase shifting said stable carrier signal in quadrature to provide quadrative phases of said carrier signal.

Claim 18

The circuit as claimed in claim 7, wherein said fourth means comprises means separately for mixing said first and second carrier signals, with said first amplified signal, to respectively provide said first intermediate base band signal for said I channel and said second mixer outputting said second intermediate base band signal for said Q channel.

Claim 19

The circuit as claimed in claim 12, wherein said second means comprises: means for dividing said recovered clock signal by two to provide a divided signal; means for filtering said divided signal; and means for amplifying the filtered signal to generate the stable carrier signal.

Claim 20

The circuit as claimed in claim 12, wherein said third means comprises means for phase shifting said stable carrier signal in quadrature to provide quadrative phases of said carrier signal.

Claim 21

The circuit as claimed in claim 12, wherein said fourth means comprises means separately for mixing said first and second carrier signals, with said first amplified signal, to respectively provide said first intermediate base band signal for said I channel and said second mixer outputting said second intermediate base band signal for said Q channel.

Claim 22

The circuit as claimed in claim 13, wherein said third means comprises means for phase shifting said stable carrier signal in quadrature to provide quadrative phases of said carrier signal.

Claim 23

The circuit as claimed in claim 13, wherein said fourth means comprises means separately for mixing said first and second carrier signals, with said first amplified signal, to respectively provide said first intermediate base band signal for said I channel and said second mixer outputting said second intermediate base band signal for said Q channel.

Claim 24

A process for receiving a code division broadcast signal having a data component mixed with a code, comprising: generating an intermediate frequency signal by down-converting a said code division broadcast signal; squaring said intermediate signal to provide a square wave signal; producing a filtered signal by filtering said square wave signal; limit-amplifying the filtered signal to provide a first amplitude-limited signal maintained at a given amplitude; generating an adjusted signal by automatically adjusting an input amplitude of said first amplitude-limited signal to exhibit a deviation in amplitude of less than a decibel value; dividing a frequency of said automatically adjusted signal by N to produce a divided frequency signal; making a comparison of said divided frequency signal with a feedback signal; producing an oscillation signal in response to said comparison; limit-amplifying said oscillation signal to provide a second amplitude-limited signal maintained at a selected amplitude; maintaining said second amplitude-limited signal at a constant amplitude; dividing a frequency of said second amplitude-limited signal by N to produce said feedback signal; dividing said frequency of said second amplitude-limited signal to produce a carrier signal; phase shifting said carrier signal, in quadrature, to produce first and secondcarrier signals and; separately mixing said amplified signal with the first carrier signal and said second carrier signal to provide said intermediate base band signals for said I and Q channels.

Claim 25

A process for receiving a code division broadcast signal having a data component mixed with a code, comprising: generating an intermediate frequency signal by down-converting a said code division broadcast signal; squaring said intermediate signal to provide a square wave signal; producing a filtered signal by filtering said square wave signal; limit-amplifying the filtered signal to provide a first amplitude-limited signal maintained at a given amplitude; generating an adjusted signal by automatically adjusting an input amplitude of said first amplitude-limited signal to exhibit a deviation in amplitude of less than a decibel value; dividing a frequency of said automatically adjusted signal by N to produce a divided frequency signal; making a comparison of said divided frequency signal with a feedback signal; producing an oscillation signal in response to said comparison; limit-amplifying said oscillation signal to provide a second amplitude-limited signal maintained at a selected amplitude; maintaining said second amplitude-limited signal at a constant amplitude; dividing a frequency of said second amplitude-limited signal by N to produce said feedback signal; dividing said frequency of said second amplitude-limited signal to produce a carrier signal; phase shifting said carrier signal, in quadrature, to produce first and secondcarrier signals and; separately mixing said amplified signal with the first carrier signal and said second carrier signal to provide said intermediate base band signals for said I and Q channels.

Claim 26

The process of claim 21, further comprised of: making said comparison by obtaining a phase difference between said divided frequency signal and said feedback signal; and producing said oscillation signal in response to said comparison.