Patent US2247375A successfully refreshed from Google Patents.
US5329482A
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Semiconductor memory device and method for producing it
Assignee: Sony Corp
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Filing: 1992-10-07
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Granted: 1994-07-12
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Expires: 2012-10-07
Abstract
Abstract In a semiconductor memory device, a first sidewall and a second sidewall are formed simultaneously for a memory cell section and a peripheral circuit section, and a high impurity concentration region is formed by being delimited by the second sidewall in the memory cell section, while a high impurity concentration section is formed by being delimited by the first sidewall in the peripheral circuit section. In this manner, MOS transistors having different LDD widths of the low impurity concentration regions and hence different characteristics, in which the MOS transistor of the memory cell section has improved voltage withstand properties and the MOS transistor of the peripheral circuit section has improved current driving capabilities, may be formed on the same substrate.
Inventors
- 👤 Hideharu Nakajima
- 👤 Hideaki Kuroda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 05:32
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
204 words
A semiconductor memory device in which a memory cell section and a peripheral circuit section are formed on one and the same substrate and in which the source regions and the drain regions of MOS transistors of said memory cell section and the peripheral circuit section consist in high concentration impurity regions and low concentration impurity regions, characterized in that each of said MOS transistors has a first sidewall formed on a lateral side of a gate electrode formed on the substrate via a gate insulating film, and a second sidewall formed on an outer side of said first sidewall, the low concentration impurity regions of the source regions and the drain regions of the MOS transistors are formed by being delimited by the ends of the gate electrodes and by the periphery of said high concentration impurity regions, the high concentration impurity regions of the source region and the drain region of the MOS transistor of said peripheral circuit section are formed by being delimited by said first sidewall, and in that the high concentration impurity regions of the source region and the drain region of the MOS transistor of said memory cell section are formed by being delimited by said second sidewall.
Claim 2
Dependent Claim
204 words
A semiconductor memory device in which a memory cell section and a peripheral circuit section are formed on one and the same substrate and in which the source regions and the drain regions of MOS transistors of said memory cell section and the peripheral circuit section consist in high concentration impurity regions and low concentration impurity regions, characterized in that each of said MOS transistors has a first sidewall formed on a lateral side of a gate electrode formed on the substrate via a gate insulating film, and a second sidewall formed on an outer side of said first sidewall, the low concentration impurity regions of the source regions and the drain regions of the MOS transistors are formed by being delimited by the ends of the gate electrodes and by the periphery of said high concentration impurity regions, the high concentration impurity regions of the source region and the drain region of the MOS transistor of said peripheral circuit section are formed by being delimited by said first sidewall, and in that the high concentration impurity regions of the source region and the drain region of the MOS transistor of said memory cell section are formed by being delimited by said second sidewall.
Claim 3
Dependent Claim
72 words
The semiconductor memory device as defined in claim 1 wherein the height of said first sidewall and said second sidewall is defined by the sum of the thicknesses of said gate insulating film, said gate electrode and the offsetting insulating film formed on said gate electrode in said memory cell section and by the sum of the thicknesses of said gate insulating film and said gate electrode in said peripheral circuit section.
Claim 4
Dependent Claim
27 words
The semiconductor memory device as defined in claim 1 wherein said gate electrode is of a polycide structure including a silicide layer formed on a polysilicon layer.
Claim 5
Dependent Claim
32 words
The semiconductor memory device as defined in claim 1 wherein said low concentration impurity region is formed of phosphorus and wherein said high concentration impurity region is formed of phosphorus and arsenic.
Claim 6
Independent Claim
168 words
A method for producing a semiconductor memory device in which a memory cell section and a peripheral circuit section are formed on one and the same substrate and in which the source regions and the drain regions of MOS transistors of said memory cell section and the peripheral circuit section consist of high concentration impurity regions and low concentration impurity regions, comprising the steps of forming a gate electrode on the substrate via a gate insulating film, forming a low concentration impurity region in self-alignment with said gate electrode, forming a first sidewall on a lateral side of said gate electrode, forming a high concentration impurity region by ion implantation only on the side of said peripheral circuit section, using said first sidewall as part of a mask, forming a second sidewall on an outer side of said first sidewall, and forming another high concentration impurity region by ion implantation only on the side of said memory cell section, using said second sidewall as part of a mask.
Claim 7
Independent Claim
168 words
A method for producing a semiconductor memory device in which a memory cell section and a peripheral circuit section are formed on one and the same substrate and in which the source regions and the drain regions of MOS transistors of said memory cell section and the peripheral circuit section consist of high concentration impurity regions and low concentration impurity regions, comprising the steps of forming a gate electrode on the substrate via a gate insulating film, forming a low concentration impurity region in self-alignment with said gate electrode, forming a first sidewall on a lateral side of said gate electrode, forming a high concentration impurity region by ion implantation only on the side of said peripheral circuit section, using said first sidewall as part of a mask, forming a second sidewall on an outer side of said first sidewall, and forming another high concentration impurity region by ion implantation only on the side of said memory cell section, using said second sidewall as part of a mask.
Claim 8
Dependent Claim
51 words
The method as defined in claim 5 wherein ion implantation for forming said low concentration impurity region is made using phosphorus as a dopant and wherein ion implantation in which said first sidewall or said second sidewall is used as part of the mask is made using arsenic as a dopant.
References Cited (Backward Citations)
US5173752A
Cited
US5091763A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-11 | 1998-01-10 | 1998-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-11 | 2002-01-10 | 2002-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-11 | 2006-01-10 | 2006-07-12 | $7700.00 | Window Closed / Lapsed |