US5327564A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Timed access system for protecting data in a central processing unit
Assignee: Maxim Integrated Products Inc
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Filing: 1991-06-13
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Granted: 1994-07-05
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Expires: 2011-06-13
Abstract
Abstract A system for protecting data in a CPU's internal register. To obtain write access to the protected register, a process must sequentially write first and second keywords to an access register, within a predetermined time window.
Inventors
- 👤 Wendell L. Little
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:49
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/14; G06F12/1458; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1689; G06F13/36; G06F13/362; G06F13/3625; G06F9/00; G06F9/06; G06F9/30; G06F9/30098; G06F9/30101
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
164 words
A protection system for protecting internal data in a CPU, comprising: a protected internal register for storing the internal data without change except when accessed, said protected register having an enable input, and being configured to allow access thereto when an enable signal is received on said enable input; access register means for receiving and storing access data; compare means, connected to said access register means, for comparing said stored access data in said access register means with a predetermined access work and outputting a true compare signal if a match exists between said predetermined access word and said stored access data; and enable timing means, connected to said enable input of said protected register, for generating said enable signal for a predetermined amount of time when said true compare signal is detected on the output of said compare means such that said protected internal register is accessible only during said predetermined time after receipt of access data corresponding to said predetermined access word.
Claim 2
Dependent Claim
164 words
A protection system for protecting internal data in a CPU, comprising: a protected internal register for storing the internal data without change except when accessed, said protected register having an enable input, and being configured to allow access thereto when an enable signal is received on said enable input; access register means for receiving and storing access data; compare means, connected to said access register means, for comparing said stored access data in said access register means with a predetermined access work and outputting a true compare signal if a match exists between said predetermined access word and said stored access data; and enable timing means, connected to said enable input of said protected register, for generating said enable signal for a predetermined amount of time when said true compare signal is detected on the output of said compare means such that said protected internal register is accessible only during said predetermined time after receipt of access data corresponding to said predetermined access word.
Claim 3
Dependent Claim
112 words
The protection system of claim 1, and further comprising: intermediate timing means for generating an intermediate period of time if a match exists between said stored access data and said predetermined access word; said compare means being connected to said intermediate timing means, and being operable to compare said stored access data with a predetermined intermediate access word and to start said intermediate timing means if a match exists between said predetermined intermediate access word and said stored access data; and said enable timing means being operable to generate said enable signal when said true compare signal output by said compare means is generated during the period of said intermediate timing means.
Claim 4
Dependent Claim
147 words
A circuit for protecting data in a register, comprising: a protected register which is sought to be protected against accidental overwriting; an access register, and a comparator connected to compare data stored in said access register with first or second predetermined access keywords and configured to output a compare signal accordingly; timed access logic, connected to receive said compare signal from said comparator, and connected to control access to said protected register; said protected register, said comparator, and said timed access logic being connected, together with at least one timing circuit, in a configuration such that said timed access logic allows access to said protected register only if said first predetermined keyword is written into said access register, AND thereafter said second predetermined keyword is written into said access register within a first predetermined maximum duration after said first predetermined keyword is written into said access register.
Claim 5
Dependent Claim
147 words
A circuit for protecting data in a register, comprising: a protected register which is sought to be protected against accidental overwriting; an access register, and a comparator connected to compare data stored in said access register with first or second predetermined access keywords and configured to output a compare signal accordingly; timed access logic, connected to receive said compare signal from said comparator, and connected to control access to said protected register; said protected register, said comparator, and said timed access logic being connected, together with at least one timing circuit, in a configuration such that said timed access logic allows access to said protected register only if said first predetermined keyword is written into said access register, AND thereafter said second predetermined keyword is written into said access register within a first predetermined maximum duration after said first predetermined keyword is written into said access register.
Claim 6
Dependent Claim
41 words
The circuit of claim 3, wherein: whenever said timed access logic allows access to said protected register, said timed access logic allows access only for a second predetermined maximum duration after said first predetermined keyword is written into said access register.
Claim 7
Dependent Claim
16 words
The circuit of claim 3, wherein said protected register is an internal register of a microprocessor.
Claim 8
Dependent Claim
20 words
The circuit of claim 3, wherein said protected register and said access register are both internal registers of a microprocessor.
Claim 9
Dependent Claim
23 words
The circuit of claim 3, wherein said protected register and said access register is an internal register of a central processing unit (CPU).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-04 | 1998-01-03 | 1998-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-04 | 2002-01-03 | 2002-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-04 | 2006-01-03 | 2006-07-05 | $7700.00 | Window Closed / Lapsed |