US5327465A
Expired / Lapsed
US
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Method and apparatus for squelch circuit in network communication
Assignee: GlobalFoundries Inc
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Filing: 1992-06-15
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Granted: 1994-07-05
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Expires: 2012-06-15
Abstract
Abstract An integrated media attachment unit (MAU) operative for interfacing Digital Terminal Equipment (DTE) on a Local Area Network (LAN) using twisted pair media. The twisted pair function as either a DTE MAU or a repeater MAU. A line driver for the twisted pair differential signal provides a ramped response with low jitter while an improved Attachment Unit Interface (AUI) driver uses CMOS technology and provides simplified End-of-Transmission Delimiter (ETD) control. The twisted pair MAU includes a combined override and status indication of link status and an additional feature to allow automatic polarity reversal of differential signal input lines and polarity status signalling.
Inventors
- 👤 John M. Wincn
- 👤 Nader Vijeh
- 👤 Ian S. Crayford
- 👤 Jeffrey M. Blumenthal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 14:14
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/0264; H04L25/028; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018557; H03K19/018571; H03K19/018578; H03K5/00; H03K5/01; H03K5/02; H03K5/023; H03K5/156; H04L25/0272; H04L25/08; H04L25/085; H04L25/38; H04L25/40; H04L25/49; H04L25/4904; H04L25/0292
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
202 words
A squelch circuit for detecting an encoded signal having a particular order of transitions of a differential signal received from a first input signal and a second input signal, comprising: a first comparator, responsive to the differential signal, for asserting a data signal if the first input signal is greater than the second input signal, otherwise; said first comparator negating said data signal if said second input signal is greater than said first input signal; a second comparator, responsive to said differential signal and including a first voltage offset at an input to said second comparator, for asserting a positive squelch signal only if said first input signal exceeds said second input signal by said first offset voltage; a third comparator, responsive to said differential signal and including a second voltage offset at an input to said third comparator, for asserting a negative squelch signal only if said second input signal exceeds said first input signal by said second offset voltage; and logic means, responsive to said data signal, said positive squelch signal and to said negative squelch signal, for asserting an unsquelch signal upon detecting a prespecified pattern of the particular order of transitions exceeding said first and second offset voltages.
Claim 2
Dependent Claim
202 words
A squelch circuit for detecting an encoded signal having a particular order of transitions of a differential signal received from a first input signal and a second input signal, comprising: a first comparator, responsive to the differential signal, for asserting a data signal if the first input signal is greater than the second input signal, otherwise; said first comparator negating said data signal if said second input signal is greater than said first input signal; a second comparator, responsive to said differential signal and including a first voltage offset at an input to said second comparator, for asserting a positive squelch signal only if said first input signal exceeds said second input signal by said first offset voltage; a third comparator, responsive to said differential signal and including a second voltage offset at an input to said third comparator, for asserting a negative squelch signal only if said second input signal exceeds said first input signal by said second offset voltage; and logic means, responsive to said data signal, said positive squelch signal and to said negative squelch signal, for asserting an unsquelch signal upon detecting a prespecified pattern of the particular order of transitions exceeding said first and second offset voltages.
Claim 3
Independent Claim
159 words
A method of asserting an unsquelch signal in response to receipt of an encoded differential signal having a particular order of transitions received from a first signal and a second signal, the method comprising the steps of: comparing the first signal to the second signal and asserting a data signal if said first signal is greater than said second signal, otherwise negating said data signal if said second signal is greater than said first signal; comparing said first signal to said second signal and asserting a positive squelch signal only if said first signal exceeds said second signal by a first offset voltage; comparing said second signal to said first signal and asserting a negative squelch signal only if said second signal exceeds said first signal by a second offset voltage; and asserting the unsquelch signal upon satisfying a prespecified combinatorial pattern of assertions and negations of said data signal, said positive squelch signal and said negative squelch signal.
Claim 4
Independent Claim
159 words
A method of asserting an unsquelch signal in response to receipt of an encoded differential signal having a particular order of transitions received from a first signal and a second signal, the method comprising the steps of: comparing the first signal to the second signal and asserting a data signal if said first signal is greater than said second signal, otherwise negating said data signal if said second signal is greater than said first signal; comparing said first signal to said second signal and asserting a positive squelch signal only if said first signal exceeds said second signal by a first offset voltage; comparing said second signal to said first signal and asserting a negative squelch signal only if said second signal exceeds said first signal by a second offset voltage; and asserting the unsquelch signal upon satisfying a prespecified combinatorial pattern of assertions and negations of said data signal, said positive squelch signal and said negative squelch signal.
Claim 5
Dependent Claim
254 words
A squelch circuit for detecting an encoded signal having a particular order of transitions of a differential signal received from a first input signal and a second input signal, comprising: a first comparator, responsive to the differential signal, for asserting a data signal if the first input signal is greater than the second input signal, otherwise; said first comparator negating said data signal if said second input signal is greater than said first input signal; a second comparator, responsive to said differential signal and including a first voltage offset at an input to said second comparator, for asserting a positive squelch signal only if said first input signal exceeds said second input signal by said first offset voltage; a third comparator, responsive to said differential signal and including a second voltage offset at an input to said third comparator, for asserting a negative squelch signal only if said second input signal exceeds said first input signal by said second offset voltage; and logic means, responsive to said data signal, said positive squelch signal and to said negative squelch signal, for asserting an unsquelch signal upon detecting a prespecified pattern of the particular order of transitions exceeding said first and second offset voltages, wherein said prespecified pattern comprises a first transition of a first type, a second transition of a second type and a third transition of said first type, with said first, second and third transitions occurring consecutively and exceeding an appropriate voltage level of said first offset voltage or said second offset voltage.
Claim 6
Dependent Claim
254 words
A squelch circuit for detecting an encoded signal having a particular order of transitions of a differential signal received from a first input signal and a second input signal, comprising: a first comparator, responsive to the differential signal, for asserting a data signal if the first input signal is greater than the second input signal, otherwise; said first comparator negating said data signal if said second input signal is greater than said first input signal; a second comparator, responsive to said differential signal and including a first voltage offset at an input to said second comparator, for asserting a positive squelch signal only if said first input signal exceeds said second input signal by said first offset voltage; a third comparator, responsive to said differential signal and including a second voltage offset at an input to said third comparator, for asserting a negative squelch signal only if said second input signal exceeds said first input signal by said second offset voltage; and logic means, responsive to said data signal, said positive squelch signal and to said negative squelch signal, for asserting an unsquelch signal upon detecting a prespecified pattern of the particular order of transitions exceeding said first and second offset voltages, wherein said prespecified pattern comprises a first transition of a first type, a second transition of a second type and a third transition of said first type, with said first, second and third transitions occurring consecutively and exceeding an appropriate voltage level of said first offset voltage or said second offset voltage.
Claim 7
Dependent Claim
23 words
The squelch circuit of claim 3 wherein said first type transition is a negative transition and said second transition is a positive transition.
Claim 8
Dependent Claim
255 words
A squelch circuit for detecting an encoded signal having a particular order of transitions of a differential signal received from a first input signal and a second input signal, comprising: a first comparator, responsive to the differential signal, for asserting a data signal if the first input signal is greater than the second input signal, otherwise; said first comparator negating said data signal if said second input signal is greater than said first input signal; a second comparator, responsive to said differential signal and including a first voltage offset at an input to said second comparator, for asserting a positive squelch signal only if said first input signal exceeds said second input signal by said first offset voltage; a third comparator, responsive to said differential signal and including a second voltage offset at an input to said third comparator, for asserting a negative squelch signal only if said second input signal exceeds said first input signal by said second offset voltage; and logic means, responsive to said data signal, said positive squelch signal and to said negative squelch signal, for asserting an unsquelch signal upon detecting a prespecified pattern of the particular order of transitions exceeding said first and second offset voltages, wherein said prespecified pattern consists of a first transition of a first type, a second transition of a second type and a third transition of said first type, with said first, second and third transitions occurring consecutively and exceeding an appropriate voltage level of said first offset voltage or said second offset voltage.
Claim 9
Dependent Claim
255 words
A squelch circuit for detecting an encoded signal having a particular order of transitions of a differential signal received from a first input signal and a second input signal, comprising: a first comparator, responsive to the differential signal, for asserting a data signal if the first input signal is greater than the second input signal, otherwise; said first comparator negating said data signal if said second input signal is greater than said first input signal; a second comparator, responsive to said differential signal and including a first voltage offset at an input to said second comparator, for asserting a positive squelch signal only if said first input signal exceeds said second input signal by said first offset voltage; a third comparator, responsive to said differential signal and including a second voltage offset at an input to said third comparator, for asserting a negative squelch signal only if said second input signal exceeds said first input signal by said second offset voltage; and logic means, responsive to said data signal, said positive squelch signal and to said negative squelch signal, for asserting an unsquelch signal upon detecting a prespecified pattern of the particular order of transitions exceeding said first and second offset voltages, wherein said prespecified pattern consists of a first transition of a first type, a second transition of a second type and a third transition of said first type, with said first, second and third transitions occurring consecutively and exceeding an appropriate voltage level of said first offset voltage or said second offset voltage.
Claim 10
Independent Claim
276 words
A method of asserting an unsquelch signal in response to receipt of an encoded differential signal having a particular order of transitions received from a first signal and a second signal, the method comprising the steps of: comparing the first signal to the second signal and asserting a data signal if said first signal is greater than said second signal, otherwise negating said data signal if said second signal is greater than said first signal; comparing said first signal to said second signal and asserting a positive squelch signal only if said first signal exceeds said second signal by a first offset voltage; comparing said second signal to said first signal and asserting a negative squelch signal only if said second signal exceeds said first signal by a second offset voltage; and asserting the unsquelch signal upon satisfying a prespecified combinatorial pattern of assertions and negations of said data signal, said positive squelch signal and said negative squelch signal; said asserting step including the steps of: asserting a first transition signal only if a negation of said data signal is substantially coincident with an assertion of said negative squelch signal; thereafter asserting a second transition signal only if an assertion of said data signal is substantially coincident with an assertion of said positive squelch signal and only if said first transition signal is asserted; thereafter asserting a third transition signal only if a negation of said data signal is substantially coincident with an assertion of said negative squelch signal and only if said second transition signal is asserted; thereafter asserting said unsquelch signal only if said third transition signal is asserted, otherwise negating said unsquelch signal.
Claim 11
Independent Claim
276 words
A method of asserting an unsquelch signal in response to receipt of an encoded differential signal having a particular order of transitions received from a first signal and a second signal, the method comprising the steps of: comparing the first signal to the second signal and asserting a data signal if said first signal is greater than said second signal, otherwise negating said data signal if said second signal is greater than said first signal; comparing said first signal to said second signal and asserting a positive squelch signal only if said first signal exceeds said second signal by a first offset voltage; comparing said second signal to said first signal and asserting a negative squelch signal only if said second signal exceeds said first signal by a second offset voltage; and asserting the unsquelch signal upon satisfying a prespecified combinatorial pattern of assertions and negations of said data signal, said positive squelch signal and said negative squelch signal; said asserting step including the steps of: asserting a first transition signal only if a negation of said data signal is substantially coincident with an assertion of said negative squelch signal; thereafter asserting a second transition signal only if an assertion of said data signal is substantially coincident with an assertion of said positive squelch signal and only if said first transition signal is asserted; thereafter asserting a third transition signal only if a negation of said data signal is substantially coincident with an assertion of said negative squelch signal and only if said second transition signal is asserted; thereafter asserting said unsquelch signal only if said third transition signal is asserted, otherwise negating said unsquelch signal.
Claim 12
Dependent Claim
63 words
The asserting method of claim 6 further comprising the steps of: clearing said first, said second and said third transition signals after said unsquelch signal has been asserted and thereafter continuing to monitor for said prespecified combinatorial pattern of said data signal, said positive sque signal and said negative squelch signal and negating said unsquelch signal if said prespecified combinatorial pattern not specified.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-04 | 1998-01-03 | 1998-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-04 | 2002-01-03 | 2002-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-04 | 2006-01-03 | 2006-07-05 | $7700.00 | Window Closed / Lapsed |