Real time video converter

Claim 2

A converter for converting a video signal from a first to a second scan rate comprising: a pixel buffer for storing a portion of the video signal having a first interlaced raster video scan rate; an address generator for determining a display location for the video signal; a non-interlaced raster frame buffer operatively connected to the pixel buffer for storing the video signal at a second scan rate differing from the first scan rate; a control sequencer operatively connected to the pixel buffer and to the address generator for providing the portion of the video signal stored in the pixel buffer and the display location to the frame buffer upon occurrence of a predetermined event; and a means for controlling in response to a user command a display size and the display location of the video signal, wherein the display is a window.

Claim 3

The device of claim 1, wherein the predetermined event is receipt of a signal from the frame buffer indicating a status of the frame buffer.

Claim 4

The device of claim 1, further comprising: a decoder for receiving a plurality of types of analog video signals; a converter for converting any of the types of analog video signals to a digital signal; and means for providing the digital signal to the pixel buffer.

Claim 5

The device of claim 3, wherein the pixel buffer stores the digital signal as twenty-four bits.

Claim 6

The device of claim 1, wherein the means for controlling a display size and location comprises: means for connecting to a processor; and user interface means operatively connectable to the process for for controlling the address generator in accordance with user commands.

Claim 7

The device of claim 1 further comprising an oscillator phase locked to a conditional timing signal in the video signal for providing a timing signal to the control sequencer.

Claim 8

The device of claim 1, further comprising means for selectively allowing a host computer to control provision of a second signal to the frame buffer.

Claim 9

The device of claim 7, wherein the means for allowing includes storage element in the frame buffer for receiving the second signal, and wherein the storage elements are operatively connected to video memory element sin the frame buffer.

Claim 10

The device of claim 1, wherein the predetermined event is receipt of a control signal from a host computer operatively connected to the control sequencer.

Claim 11

A converter for converting scan rates of video signals comprising: a pixel buffer for storing a portion of a video signal having a first scan rate which is that of an interlaced raster scan; an address generator for determining a display location for the first video signal; a non-interlaced raster frame buffer operatively connected to the buffer for storing video signals at a second scan rate differing from the first scan rate; a control sequencer operatively connected to the pixel buffer and to the address generator for providing the portion of the video signal stored in the pixel buffer and the display location to the frame buffer in real time upon receipt of a signal from the frame buffer indicating a status of the frame buffer, and upon receipt of a control signal from a host computer; means for providing a second video data signal under control of a host computer directly from an external source to the frame buffer; and means for determining whether the video signal or second video data signal is to be provided to the frame buffer at any particular time.

Claim 12

A converter for converting scan rates of video signals comprising: a pixel buffer for storing a portion of a video signal having a first scan rate which is that of an interlaced raster scan; an address generator for determining a display location for the first video signal; a non-interlaced raster frame buffer operatively connected to the buffer for storing video signals at a second scan rate differing from the first scan rate; a control sequencer operatively connected to the pixel buffer and to the address generator for providing the portion of the video signal stored in the pixel buffer and the display location to the frame buffer in real time upon receipt of a signal from the frame buffer indicating a status of the frame buffer, and upon receipt of a control signal from a host computer; means for providing a second video data signal under control of a host computer directly from an external source to the frame buffer; and means for determining whether the video signal or second video data signal is to be provided to the frame buffer at any particular time.

Claim 15

The method of claim 11, further comprising, prior to the step of storing, the steps of: providing a plurality of analog video signals each being of a different television standard; and converting each of the plurality of analog video signals to a digital signal.

Claim 16

The device of claim 1, further comprising means for providing to the buffer video signals of any one of a plurality of television standards.

Claim 17

A converter for converting from a first video signal to a second scan rate comprising: a buffer for storing a portion of the video signal having a first scan rate; an address generator for determining a display location for the video signal; a frame buffer operatively connected to the buffer for storing the video signal at a second scan rate differing from the first scan rate; means for selectively providing, under control of a host computer, a second video data signal from an external source directly to a dedicated port of the frame buffer; a control sequencer operatively connected to the buffer and to the address generator for providing the portion of the video signal stored in said buffer and the display location to the frame buffer upon occurrence of a predetermined event; and means for providing the portion of the video signal in the frame buffer to the display at the display location.

Claim 18

A converter for converting from a first video signal to a second scan rate comprising: a buffer for storing a portion of the video signal having a first scan rate; an address generator for determining a display location for the video signal; a frame buffer operatively connected to the buffer for storing the video signal at a second scan rate differing from the first scan rate; means for selectively providing, under control of a host computer, a second video data signal from an external source directly to a dedicated port of the frame buffer; a control sequencer operatively connected to the buffer and to the address generator for providing the portion of the video signal stored in said buffer and the display location to the frame buffer upon occurrence of a predetermined event; and means for providing the portion of the video signal in the frame buffer to the display at the display location.

Claim 21

The device of claim 14, wherein the second video data signal to the frame buffer includes address and control signals from the host computer.

Claim 22

The device of claim 10, further comprising: means for controlling in response to a user command or display size and the display location of the video signal, wherein the display is a window.

Claim 23

The device of claim 17, wherein the means for controlling comprises: means for connecting to a processor; and user interface means operatively connectable to the process for for controlling the address generator in accordance with user command.

Claim 24

The device of claim 10, wherein the second video data signal to the frame buffer includes address and control signals from the host computer.

Claim 25

The method of claim 11, further comprising, in the step of selectively providing: providing address and control portions of the second video data signal to a dedicated port of the frame buffer from the host computer.

Claim 26

The device of claim 15, wherein the second video data signal to the frame buffer includes address and control signals from the host computer.

Claim 27

The method of claim 11, further comprising the step of providing control from a user over the location.

Claim 28

The device of claim 10, wherein the raster frame buffer includes a port for receipt of the second video data signal directly from the external source.