Multiple ramp procedure with higher order noise shaping

Claim 1

An analog to digital converter according to a multiple-ramp procedure for performing continuous integration of an input signal (9) applied thereto, comprising a summation circuit (1) having a first input connected to said input signal (9); a charge storage circuit (2) having an input connected to an output of said summation circuit (1), a comparator circuit (3), with a switching threshold, having an input connected to an output (13) of the charge storage circuit (2), and generating a comparator output signal (16); a logic circuit (5) evaluating said comparator output signal, at least two analog switching control lines (17) connected to respective outputs of said logic circuit (5); a clock oscillator (6) applying a clock signal (14) to an input of said logic circuit (5); and a switching circuit (7) applying, as an input signal to said charge storage circuit (2), at least one of a first reference signal (r1) and a second reference signal (r2), as determined by control inputs connected via said analog switching control lines (17) to said respective outputs of said logic circuit (5), wherein said comparator circuit (3) responds to an input signal (13) which crosses its switching threshold by producing a comparator output signal which triggers cessation of application of a currently applied one of said reference signals (r1,r2) and, at a predefined time with respect thereto, resumption of application of a different one of said reference signals (r1,r2), said triggering occurring in said logic circuit (5) at periodically recurrent time intervals at an edge of said clock oscillator output signal (14); said logic circuit (5) generates an output signal (12), corresponding values of said summation circuit input signal (9) and said logic circuit output signal (12) collectively defining a transfer function H(z) of said analog-to-digital converter; wherein, whenever at least one of said first and second reference signals (r1,r2) is zero, said transfer function H(z) has an Nth order, N≧1, low-pass filter characteristic; `those instants when one of said reference signals is applied to said summation circuit (2) are defined as a "switched-on state" and said reference signal, and the duration of the switched-on state of the reference signal in a settled-down state and neglecting quantization noise, is a linear function of the input signal (9), and wherein a quantization noise transfer function H.sub.q (z)=1/(1+H(z)) has a high-pass filter characteristic, thereby achieving greatest possible suppression of quantization noise in the frequency range of the input signal (9) being converted in said analog-to-digital converter.