US5325183A
Expired / Lapsed
US
⏱️ 0.0 years remaining
OSD circuit for displaying advertising picture data
Assignee: Samsung Electronics Co Ltd
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Filing: 1992-08-17
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Granted: 1994-06-28
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Expires: 2012-08-17
Abstract
Abstract An OSD circuit for displaying advertising picture data on the screen of a television receiver is disclosed, and the circuit includes: an oscillator, a first counter, a second counter, a third counter, an F/F circuit, a ROM, and automatic color adjusting circuitry. The oscillator supplies clock signals to the first counter, and the first and second counters supplies horizontal and vertical scanning addresses to the ROM so as for the advertising picture data to be outputted from the ROM. The third counter, supplies a delay signal for displaying of an advertising picture data of a picture scene at a time, thereby inhibiting the output of the ROM for a certain period of time. The F/F circuit prevents a dual display of the advertising picture on the screen, and the ROM stores the advertising picture data separately for main color data, first sub-color data, second sub-color data and brightness data. The automatic color adjusting circuitry receives the advertising data consisting of the main color data, the first sub-color data and the second sub-color data from the ROM, and supplies an advertising picture having a color definitely contrasting to the color of the picture of the currently broadcasting program. If the OSD circuit of the present invention is applied to television receivers, not only advertising picture data can be continuously displayed for a certain period of time in a successive manner, but also a clear and harmonized picture color can be obtained.
Inventors
- 👤 Pil G. Rhee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:27
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/64; H04N9/641; H04N5/00; H04N5/44; H04N5/445; H04N21/00; H04N21/40; H04N21/47; H04N21/478
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
288 words
An OSD circuit for displaying picture data on the screen of a television receiver, comprising: a signal generator for generating signals synchronized with horizontal synchronizing signals from a received video signal, and for supplying the generated signals as clock signals to a first counter; said first counter generating horizontal scanning addresses to memories by counting said clock signals, and being cleared upon receipt of a subsequent horizontal synchronizing signal so the horizontal scanning address returns to its initial value; a second counter for generating vertical scanning addresses by counting said horizontal synchronizing signals in order to supply them to said memories, and being cleared upon receipt of a vertical synchronizing signal of said received video signal so the vertical scanning address returns to its initial value; a third counter for generating delay signals required for displaying a data block of one picture scene for a particular period of time on the screen by counting the vertical synchronizing signals, and for supplying the delay signals to said memories thereby causing said memories to output the data block; said third counter being cleared upon receipt of a power-on signal to select said memories in a predetermined sequence, and thereby causing data block data to be output in a predetermined sequence; a flip-flop circuit for generating disabling signals to said memories in response to carry signals after receipt of the carry signals form said first counter to prevent a dual display of the picture data; and an automatic color adjuster for selecting picture data from said memories contrasting to the colors of the picture of the currently received video signal; wherein said memories store said picture data separately as main color data, first sub-color data, second sub-color data, and brightness data.
Claim 2
Dependent Claim
288 words
An OSD circuit for displaying picture data on the screen of a television receiver, comprising: a signal generator for generating signals synchronized with horizontal synchronizing signals from a received video signal, and for supplying the generated signals as clock signals to a first counter; said first counter generating horizontal scanning addresses to memories by counting said clock signals, and being cleared upon receipt of a subsequent horizontal synchronizing signal so the horizontal scanning address returns to its initial value; a second counter for generating vertical scanning addresses by counting said horizontal synchronizing signals in order to supply them to said memories, and being cleared upon receipt of a vertical synchronizing signal of said received video signal so the vertical scanning address returns to its initial value; a third counter for generating delay signals required for displaying a data block of one picture scene for a particular period of time on the screen by counting the vertical synchronizing signals, and for supplying the delay signals to said memories thereby causing said memories to output the data block; said third counter being cleared upon receipt of a power-on signal to select said memories in a predetermined sequence, and thereby causing data block data to be output in a predetermined sequence; a flip-flop circuit for generating disabling signals to said memories in response to carry signals after receipt of the carry signals form said first counter to prevent a dual display of the picture data; and an automatic color adjuster for selecting picture data from said memories contrasting to the colors of the picture of the currently received video signal; wherein said memories store said picture data separately as main color data, first sub-color data, second sub-color data, and brightness data.
Claim 3
Dependent Claim
227 words
The OSD circuit as claimed in claim 1, wherein said automatic color adjuster comprises: a multiplexer for selecting signals one-by-one from R, G and B signals of said received video signals through R, G and B lines under control of the delay signals of said third counter, in order to supply them to a sample/hold circuit; said sample/hold circuit sampling the R, G and B signals after receipt from said multiplexer in order to send the sampled signals to an integrator; said sample/hold circuit holding the picture data being sent to said R, G and B lines so the data is not read during the sampling upon receipt of a hold signal, said hold signal being formed by a sum of a blanking signal form said second counter and a signal from said flip-flop circuit; said integrator extracting R, G and B average value signals from the sampled signals; R-G, G-B and B-R comparators for comparing magnitudes of the R, G, and B extracted average value signals, and for outputting the compared data to a data selector; said data selector combining the compared data from said comparators; and said data selector sending the combined picture data to said R, G and B lines, thereby having clear and harmonized colors contrasting to the colors of the picture of said received video signal, and thereby forming an OSD picture.
Claim 4
Dependent Claim
386 words
The OSD circuit data as claimed in claim 5, wherein said data selector comprises a logic array defining logic formulas for the R, G and B color data of the picture data specified as: __________________________________________________________________________
R out = A & ((R < G & G < B & B < R) + (R < G & G < B & B < R))
+ B & ((R < G & G < B & B < R) + (R < G & G < B & B < R))
+ C & ((R < G & G < B & B < R) + (R < G & G < B & B < R))
G out = A & ((R < G & G < B & B < R) + (R < G & G < B & B < R))
+ B & ((R < G & G < B & B < R) + (R < G & G < B & B < R))
+ C & ((R < G & G < B & B < R) + (R < G & G < B & B < R))
B out = A & ((R < G & G < B & B < R) + (R < G & G < B & B < R))
+ B & ((R < G & G < B & B < R) + (R < G & G < B & B < R))
+ C & ((R < G & G < B & B < R) + (R < G & G < B & B < R))
__________________________________________________________________________ where R<G is the output value of said R-G comparator; G<B is the output value of said G-B comparator; B<R is the output value of said B-R comparator; A is the value of the main color data supplied from said memories; B is the value of the first sub-color data supplied from said memories; C is the value of the second color data supplied from said memories; R out is the values of the R signals outputted to said R line; G out is the values of the G signals outputted to said G line; and B out is the values of the B signals outputted to said B line.
References Cited (Backward Citations)
US4170023A
Cited
US4455554A
Cited
US4507683A
Cited
US4746980A
Cited
US4951126A
Cited
US4821102A
Cited
US5065346A
Cited
JPS6412887A
Cited
US5072214A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-27 | 1997-12-27 | 1998-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-27 | 2001-12-27 | 2002-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-27 | 2005-12-27 | 2006-06-28 | $7700.00 | Window Closed / Lapsed |