US5323399A
Expired / Lapsed
US
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ATM cell multiplexing device capable of reducing an accessing speed to a FIFO memory thereof
Assignee: NEC Corp
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Filing: 1992-03-30
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Granted: 1994-06-21
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Expires: 2012-03-30
Abstract
Abstract On time division multiplexing first through N-th input signals, each having a bit rate V to represent successive ATM cells, a multiplexing section (12, 13') multiplexes the first through the N-th input signals and a dummy input signal into a time division multiplexed signal having another bit rate V×(N+1) and comprising first through N-th multiplexed cells and a dummy multiplexed cell. The first through the N-th and the dummy multiplexed cells are derived from the first through the N-th and the dummy input signals, respectively. A controller (16') successively writes valid cells of the first through the N-th multiplexed cells in an FIFO memory (15) as written cells at a writing rate equal to the bit rate V×(N+1) for a writing time interval defined by the first through the N-th multiplexed cells and reads the written cells from the FIFO memory in a first-in first-out order as a read-out signal at a reading rate equal to the bit rate V×(N+1) for a reading time interval defined by the dummy multiplexed cell. A converter (17) converts the read-out signal into a multiplexed output signal having the bit rate V.
Inventors
- 👤 Takatoshi Kurano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:33
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L49/00; H04L49/10; H04L49/104; H04L49/105; H04L49/107; H04L2012/5672; H04L2012/5678; H04L2012/5681
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
384 words
An ATM cell multiplexing device comprising: first through N-th input lines supplied with first through N-th input signals, each having a predetermined bit rate V and representing successive ATM cells classifiable into valid cells and invalid cells, where N represents an integer greater than one; an output line; and processing means connected to said first through said N-th input lines and to said output line for processing said first through said N-th input signals into a time division multiplexed output signal having said predetermined bit rate V, said processing means being for delivering said time division multiplexed output signal to said output line; wherein said processing means includes an additional input line supplied with an additional input signal having said predetermined bit rate V and representing successive additional cells, each of which is identical with said invalid cells; time division multiplexing means connected to said first through said N-th input lines and said additional input line for time division multiplexing said first through said N-th input signals and said additional input signal into a time division multiplexed signal having a prescribed bit rate V×(N+1) and comprising first through N-th multiplexed cells and an additional multiplexed cell, said first through said N-th multiplexed cells and said additional multiplexed cell being derived from said first through said N-th input signals and said dummy input signal, respectively; a first-in first-out memory connected to said time division multiplexing means; controlling means connected to said time division multiplexing means and to said first-in first-out memory for controlling said first-in first-out memory to successively write said valid cells of said first through said N-th multiplexed cells in said first-in first-out memory as written cells at a writing rate equal to said prescribed bit rate V×(N+1) for a writing time interval defined by said first through said N-th multiplexed cells and to read said written cells out of said first-in first-out memory in a first-in first-out order as a read-out signal at a reading rate equal to said prescribed bit rate V×(N+1) for a reading time interval defined by said additional multiplexed cell; and converting means connected to said first-in first-out memory and to said output line for converting said read-out signal into said time division multiplexed output signal to deliver said time division multiplexed output signal to said output line.
Claim 2
Dependent Claim
384 words
An ATM cell multiplexing device comprising: first through N-th input lines supplied with first through N-th input signals, each having a predetermined bit rate V and representing successive ATM cells classifiable into valid cells and invalid cells, where N represents an integer greater than one; an output line; and processing means connected to said first through said N-th input lines and to said output line for processing said first through said N-th input signals into a time division multiplexed output signal having said predetermined bit rate V, said processing means being for delivering said time division multiplexed output signal to said output line; wherein said processing means includes an additional input line supplied with an additional input signal having said predetermined bit rate V and representing successive additional cells, each of which is identical with said invalid cells; time division multiplexing means connected to said first through said N-th input lines and said additional input line for time division multiplexing said first through said N-th input signals and said additional input signal into a time division multiplexed signal having a prescribed bit rate V×(N+1) and comprising first through N-th multiplexed cells and an additional multiplexed cell, said first through said N-th multiplexed cells and said additional multiplexed cell being derived from said first through said N-th input signals and said dummy input signal, respectively; a first-in first-out memory connected to said time division multiplexing means; controlling means connected to said time division multiplexing means and to said first-in first-out memory for controlling said first-in first-out memory to successively write said valid cells of said first through said N-th multiplexed cells in said first-in first-out memory as written cells at a writing rate equal to said prescribed bit rate V×(N+1) for a writing time interval defined by said first through said N-th multiplexed cells and to read said written cells out of said first-in first-out memory in a first-in first-out order as a read-out signal at a reading rate equal to said prescribed bit rate V×(N+1) for a reading time interval defined by said additional multiplexed cell; and converting means connected to said first-in first-out memory and to said output line for converting said read-out signal into said time division multiplexed output signal to deliver said time division multiplexed output signal to said output line.
Claim 3
Dependent Claim
468 words
An ATM cell multiplexing device comprising: first through M-th output lines having output line numbers different from each other, where M represents a natural number greater than one; first through N-th input lines supplied with first through N-th input signals, each having a predetermined bit rate V and representing successive ATM cells classifiable into valid cells and invalid cells, each of said valid cells having a destination address representative of one of said output line numbers, where N represents an integer greater than one; an additional input line supplied with an additional input signal having said predetermined bit rate V and representing successive additional cells, each of which is identical with said invalid cells; time division multiplexing means connected to said first through said N-th input lines and said additional input line for time division multiplexing said first through said N-th input signals and said additional input signal into a time division multiplexed signal having a prescribed bit rate V×(N+1) and comprising first through N-th multiplexed cells and an additional multiplexed cell, said first through said N-th multiplexed cells and said additional multiplexed cell being derived from said first through said N-th input signals and said additional input signal, respectively; first through M-th first-in first-out memories corresponding to said first through said M-th output lines and connected to said time division multiplexing means; controlling means connected to said time division multiplexing means and to said first through said M-th first-in first-out memories for controlling said first through said M-th first-in first-out memories to successively write said valid cells of said first through said N-th multiplexed cells in corresponding ones of said first through said M-th first-in first-out memories as written cells at a writing rate equal to said prescribed bit rate V×(N+1) for a writing time interval defined by said first through said N-th multiplexed cells and to read said written cells out of said first through said M-th first-in first-out memories in a first-in first-out order as first through M-th read-out signals at a reading rate equal to said prescribed bit rate V×(N+1) for a reading time interval defined by said additional multiplexed cell, each of said corresponding ones of said first through said M-th first-in first-out memories corresponding to one of said first through said M-th output lines that has an output line number represented by a designation address of each of said valid cells of said first through said N-th multiplexed cells; and first through M-th converting means connected to said first through said M-th first-in first-out memories and to said first through said M-th output lines for converting said first through said M-th read-out signals into first through M-th time division multiplexed output signals to deliver said first through M-th time division multiplexed output signals to said first through said M-th output lines, respectively.
Claim 4
Dependent Claim
468 words
An ATM cell multiplexing device comprising: first through M-th output lines having output line numbers different from each other, where M represents a natural number greater than one; first through N-th input lines supplied with first through N-th input signals, each having a predetermined bit rate V and representing successive ATM cells classifiable into valid cells and invalid cells, each of said valid cells having a destination address representative of one of said output line numbers, where N represents an integer greater than one; an additional input line supplied with an additional input signal having said predetermined bit rate V and representing successive additional cells, each of which is identical with said invalid cells; time division multiplexing means connected to said first through said N-th input lines and said additional input line for time division multiplexing said first through said N-th input signals and said additional input signal into a time division multiplexed signal having a prescribed bit rate V×(N+1) and comprising first through N-th multiplexed cells and an additional multiplexed cell, said first through said N-th multiplexed cells and said additional multiplexed cell being derived from said first through said N-th input signals and said additional input signal, respectively; first through M-th first-in first-out memories corresponding to said first through said M-th output lines and connected to said time division multiplexing means; controlling means connected to said time division multiplexing means and to said first through said M-th first-in first-out memories for controlling said first through said M-th first-in first-out memories to successively write said valid cells of said first through said N-th multiplexed cells in corresponding ones of said first through said M-th first-in first-out memories as written cells at a writing rate equal to said prescribed bit rate V×(N+1) for a writing time interval defined by said first through said N-th multiplexed cells and to read said written cells out of said first through said M-th first-in first-out memories in a first-in first-out order as first through M-th read-out signals at a reading rate equal to said prescribed bit rate V×(N+1) for a reading time interval defined by said additional multiplexed cell, each of said corresponding ones of said first through said M-th first-in first-out memories corresponding to one of said first through said M-th output lines that has an output line number represented by a designation address of each of said valid cells of said first through said N-th multiplexed cells; and first through M-th converting means connected to said first through said M-th first-in first-out memories and to said first through said M-th output lines for converting said first through said M-th read-out signals into first through M-th time division multiplexed output signals to deliver said first through M-th time division multiplexed output signals to said first through said M-th output lines, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-20 | 1997-12-20 | 1998-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-20 | 2001-12-20 | 2002-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-20 | 2005-12-20 | 2006-06-21 | $7700.00 | Window Closed / Lapsed |