US5323043A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS integrated circuit
Assignee: NEC Corp
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Filing: 1993-01-13
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Granted: 1994-06-21
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Expires: 2013-01-13
Abstract
Abstract A first shallow well 5, a second shallow well 3, a third deep well 4, a fourth shallow well 5' and a fifth shallow well 2 are formed on an electroconductive substrate 1, in which a first and second digital series power supplies DVDD, DVSS are each connected to the first shallow well 5 completely included by the third deep well 4 and the second shallow well 3 partially included by the third deep well 4 respectively, a first and second analog series power supplies AVDD, AVSS are each connected to the fourth and fifth shallow wells 5', 2 not included by the third deep well 4 respectively, a MOS transistor constituting a digital circuit is formed on the surface of the first and second shallow wells 5, 3 to which the digital series power supply is connected and a MOS transistor constituting an analog circuit is formed on the surface of the fourth and fifth shallow wells 5', 2 to which the analog series power supply is connected. As a result, it can be effectively prevented at a low cost for the digital noise of the CMOS integrated circuit mixedly loading the analog and digital circuits from being backfired to the analog circuit.
Inventors
- 👤 Madoka Kimura
- 👤 Yoshio Miyazaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:52
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; H10D89/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
248 words
A CMOS integrated circuit on which an analog CMOS circuit and a digital CMOS circuit appear, said CMOS integrated circuit comprising: a first p-type well and second n-type well which are each formed on a p-type substrate; a third n-type well having a greater depth than said first and second wells, said second and third wells partially overlapping each other, said first well being surrounded by a region comprised of said second and third wells; a first and second digital series power supplies each connected to said first and second wells, respectively, for imparting low and high potentials, respectively; a fourth p-type well and fifth n-type well which are each formed on said substrate, remote from said third well; a first and second analog series power supplies each connected to said fourth and fifth wells, respectively, for imparting low and high potentials, respectively; a first n-channel MOS transistor being part of said digital CMOS circuit, said first n-channel MOS transistor being formed on the surface of said first well; a first p-channel MOS transistor being part of said digital CMOS circuit, said first p-channel MOS transistor being formed on the surface of said second well; a second n-channel MOS transistor being part of said analog CMOS circuit, said second n-channel MOS transistor being formed on the surface of said fourth well; and a second p-channel MOS transistor being part of said analog CMOS circuit, said second p-channel MOS transistor being formed on the surface of said fifth well.
Claim 2
Dependent Claim
248 words
A CMOS integrated circuit on which an analog CMOS circuit and a digital CMOS circuit appear, said CMOS integrated circuit comprising: a first p-type well and second n-type well which are each formed on a p-type substrate; a third n-type well having a greater depth than said first and second wells, said second and third wells partially overlapping each other, said first well being surrounded by a region comprised of said second and third wells; a first and second digital series power supplies each connected to said first and second wells, respectively, for imparting low and high potentials, respectively; a fourth p-type well and fifth n-type well which are each formed on said substrate, remote from said third well; a first and second analog series power supplies each connected to said fourth and fifth wells, respectively, for imparting low and high potentials, respectively; a first n-channel MOS transistor being part of said digital CMOS circuit, said first n-channel MOS transistor being formed on the surface of said first well; a first p-channel MOS transistor being part of said digital CMOS circuit, said first p-channel MOS transistor being formed on the surface of said second well; a second n-channel MOS transistor being part of said analog CMOS circuit, said second n-channel MOS transistor being formed on the surface of said fourth well; and a second p-channel MOS transistor being part of said analog CMOS circuit, said second p-channel MOS transistor being formed on the surface of said fifth well.
Claim 3
Dependent Claim
21 words
A CMOS integrated circuit as set forth in claim 1 wherein a part of said substrate functions as said fourth well.
Claim 4
Dependent Claim
245 words
A CMOS integrated circuit on which an analog CMOS circuit and a digital CMOS circuit are loaded, comprising: a first n-type well and second p-type well which are each formed on an n-type substrate; a third p-type well having a greater depth than said first and second wells, said second and third wells partially overlapping each other, said first well being surrounded by a region comprised of said second and third wells; a first and second digital series power supplies each connected to said first and second wells, respectively, for imparting high and low potentials, respectively; a fourth n-type well and fifth p-type well which are each formed on said substrate, remote from said third well; a first and second analog series power supplies each connected to said fourth and fifth wells, respectively, for imparting high and low potentials, respectively; a first p-channel MOS transistor being part of said digital CMOS circuit, said first p-channel MOS transistor being formed on the surface of said first well; a first n-channel MOS transistor being part of said digital CMOS circuit, said first n-channel MOS transistor being formed on the surface of said second well; a second p-channel MOS transistor being part of said analog CMOS circuit, said second p-channel MOS transistor being formed on the surface of said fourth well; and a second n-channel MOS transistor being part of said analog CMOS circuit, said second n-channel MOS transistor being formed on the surface of said fifth well.
Claim 5
Dependent Claim
245 words
A CMOS integrated circuit on which an analog CMOS circuit and a digital CMOS circuit are loaded, comprising: a first n-type well and second p-type well which are each formed on an n-type substrate; a third p-type well having a greater depth than said first and second wells, said second and third wells partially overlapping each other, said first well being surrounded by a region comprised of said second and third wells; a first and second digital series power supplies each connected to said first and second wells, respectively, for imparting high and low potentials, respectively; a fourth n-type well and fifth p-type well which are each formed on said substrate, remote from said third well; a first and second analog series power supplies each connected to said fourth and fifth wells, respectively, for imparting high and low potentials, respectively; a first p-channel MOS transistor being part of said digital CMOS circuit, said first p-channel MOS transistor being formed on the surface of said first well; a first n-channel MOS transistor being part of said digital CMOS circuit, said first n-channel MOS transistor being formed on the surface of said second well; a second p-channel MOS transistor being part of said analog CMOS circuit, said second p-channel MOS transistor being formed on the surface of said fourth well; and a second n-channel MOS transistor being part of said analog CMOS circuit, said second n-channel MOS transistor being formed on the surface of said fifth well.
Claim 6
Dependent Claim
20 words
CMOS integrated circuit as set forth in claim 3 wherein a part of said substrate functions as said fourth well.
References Cited (Backward Citations)
US4907058A
Cited
US5146112A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-20 | 1997-12-20 | 1998-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-20 | 2001-12-20 | 2002-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-20 | 2005-12-20 | 2006-06-21 | $7700.00 | Window Closed / Lapsed |