US5321818A
Expired / Lapsed
US
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System for arbitrating for access on VME bus structures
Assignee: Raytheon Co
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Filing: 1992-05-12
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Granted: 1994-06-14
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Expires: 2012-05-12
Abstract
Abstract System for providing self-selection arbitration among a plurality of slave processors connected to a VME back plane. The slave processors are connected to a common ID bus, interrupt line, and acknowledge bus. Slave processors contend for access to the VME back plane by asserting an interrupt level unique to a group of slave processors on the interrupt line. Simultaneously, the contending slave processors apply their respective addresses to the ID bus. When a contending slave processor receives an acknowledge over the acknowledge bus from a master processor, and senses its own address on the ID bus, it has successfully won the right to transmit data over the data bus.
Inventors
- 👤 Daniel R. Wendling
- 👤 Michael J. Giovannoni
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:13
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/36; G06F13/368; G06F13/374
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
159 words
A system for interconnecting a plurality of salve processors to a master processor over a VME bus structure, permitting data transfers over data lines and address lines of said bus structure, comprising: a first group of said slave processors connected to a first common interrupt bus, and an IACK bus of said VME bus structure, and to a first common ID bus; a second group of said slave processors interconnected to a second common interrupt bus, and to said IACK bus of said VME bus structure, and connected to a second common ID bus; and, a master processor connected to said first and second common interrupt buses of said VME buses, responsive to at least two interrupt levels, said master processor initiating an ACKNOWLEDGE to one of said groups of slave processors over said IACK bus which initiates an INTERRUPT, authorizing said one group to permit one of a respective slave processors access to said VME bus data lines.
Claim 2
Independent Claim
159 words
A system for interconnecting a plurality of salve processors to a master processor over a VME bus structure, permitting data transfers over data lines and address lines of said bus structure, comprising: a first group of said slave processors connected to a first common interrupt bus, and an IACK bus of said VME bus structure, and to a first common ID bus; a second group of said slave processors interconnected to a second common interrupt bus, and to said IACK bus of said VME bus structure, and connected to a second common ID bus; and, a master processor connected to said first and second common interrupt buses of said VME buses, responsive to at least two interrupt levels, said master processor initiating an ACKNOWLEDGE to one of said groups of slave processors over said IACK bus which initiates an INTERRUPT, authorizing said one group to permit one of a respective slave processors access to said VME bus data lines.
Claim 3
Dependent Claim
60 words
The system of claim 1 wherein slave processors of a group each include means for asserting their respective addresses on said first common ID bus when access to said VME bus is desired, and means for determining from the address data on said ID bus whether or not priority over other slave processors asserting an address on said bus exits.
Claim 4
Dependent Claim
44 words
The system of claim 2 wherein each of said processors contending for access to said VME bus includes means for detecting its own address on a respective ID bus, the presence of which identifies that said slave has priority access to said VME bus.
Claim 5
Dependent Claim
41 words
The system of claim 3 wherein said slave processors are arranged in priority by assigning addresses to higher priority slave processors which can over-write an address of a lesser priority slave processor when both are simultaneously applied to said ID bus.
Claim 6
Dependent Claim
25 words
The system of claim 1 wherein each group of said slave processors has a unique interrupt level which can be handled by said master processor.
Claim 7
Independent Claim
140 words
A method for interconnecting a plurality of slave processors over a VME back plane with a master processor comprising: connecting a first group of said slave processors to a first common interrupt bus, and an IACK bus of said back plane and to a first ID bus; sensing at a master processor an interrupt level unique to one of said groups asserted by one or more slave processors of one of said groups of slave processors on a respective interrupt bus; initiating from said master processor encoded IACK data on said IACK bus identifying that said one group of slave processors which initiated said interrupt level may initiate a data transfer over said back plane; and, arbitrating among said slave processors of said group to permit one of said slave processors to initiate data transmission over said VME back plane.
Claim 8
Independent Claim
140 words
A method for interconnecting a plurality of slave processors over a VME back plane with a master processor comprising: connecting a first group of said slave processors to a first common interrupt bus, and an IACK bus of said back plane and to a first ID bus; sensing at a master processor an interrupt level unique to one of said groups asserted by one or more slave processors of one of said groups of slave processors on a respective interrupt bus; initiating from said master processor encoded IACK data on said IACK bus identifying that said one group of slave processors which initiated said interrupt level may initiate a data transfer over said back plane; and, arbitrating among said slave processors of said group to permit one of said slave processors to initiate data transmission over said VME back plane.
Claim 9
Dependent Claim
86 words
The method of interconnecting a plurality of slave processors over a VME back plane with a master processor according to claim 6 wherein said step of arbitrating among said slave processors comprises: asserting an address of each slave processor which contends for access to said back plane on a respective ID bus; sensing the address on said respective ID bus by each contending slave processor and, each contending slave processor yielding priority to a slave processor whose address overwrites any other address on said ID bus.
Claim 10
Dependent Claim
48 words
The method of claim 7 wherein each slave processor contending for access to said VME back plane simultaneously asserts its address on said ID bus while sensing said ID data bus lines, and transmits said data over said back plane when the slave processor senses its own address.
Claim 11
Dependent Claim
159 words
In a system of a group of slave processors interconnected over a VME back plane to a master processor, an arbitration circuit for each of said slave processors comprising: an interrupt generator at each slave processor for generating an interrupt level on an interrupt line connecting said slave processors to a master processor; an address driver at each slave processor for asserting a unique address associated with said slave processor on an ID bus; means at each slave processor for sensing an address on said ID bus; a comparator at each slave processor for detecting the simultaneous occurrence of an interrupt acknowledge signal issued by a master processor in response to said interrupt level, with the presence of said unique address on said ID bus; and, means for enabling a data transmission from a slave processor when a respective comparator identifies the presence of said slave processor address on said bus and the presence of said interrupt acknowledge signal.
Claim 12
Dependent Claim
159 words
In a system of a group of slave processors interconnected over a VME back plane to a master processor, an arbitration circuit for each of said slave processors comprising: an interrupt generator at each slave processor for generating an interrupt level on an interrupt line connecting said slave processors to a master processor; an address driver at each slave processor for asserting a unique address associated with said slave processor on an ID bus; means at each slave processor for sensing an address on said ID bus; a comparator at each slave processor for detecting the simultaneous occurrence of an interrupt acknowledge signal issued by a master processor in response to said interrupt level, with the presence of said unique address on said ID bus; and, means for enabling a data transmission from a slave processor when a respective comparator identifies the presence of said slave processor address on said bus and the presence of said interrupt acknowledge signal.
Claim 13
Dependent Claim
27 words
The system of claim 9 wherein said slave processor shares with second a group of slave processors, a common ID bus, interrupt acknowledge bus, and interrupt line.
Claim 14
Dependent Claim
33 words
The system of claim 9 wherein a slave processor has a priority among other slave processors depending on its ability to overwrite the address of said other slave processors on said ID bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-13 | 1997-12-13 | 1998-06-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-13 | 2001-12-13 | 2002-06-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-13 | 2005-12-13 | 2006-06-14 | $7700.00 | Window Closed / Lapsed |