Bilayer photolithographic process

Claim 2

A process for creating a mask on the surface of an integrated circuit workpiece, comprising the steps of: applying a first layer of resist to the surface of the workpiece; exposing an upper surface of the first layer to an organometallic compound; responsive to said step of exposing, metallizing an upper portion of the first layer, a lower portion of the first layer remote from the upper surface left unmetallized; applying a second layer of resist to the upper surface of the first layer, the second layer being photosensitive to at least one preselected wavelength of light; selectively exposing the second layer to the preselected wavelength; developing the selectively exposed second layer to create orifices in the second layer and uncover respective areas of the metallized upper portion of the first layer; using the developed second layer as a mask, etching the respective areas of the metallized upper portion of the first layer using an etchant which removes said metallized upper portion but does not remove said unmetallized lower portion to expose respective areas of the lower portion of the first layer; and using the etched metallized upper portion as a mask, etching lower portion of the first layer to expose respective portions of the surface of the workpiece.

Claim 3

The process of claim 1, wherein said organometallic compound is an organosilicon compound and wherein the metallized upper portion is silylated.

Claim 4

The process of claim 2, wherein said organosilicon compound is selected from the group consisting of allyltrimethylsilane (ATMS), hexamethyldisilane (HMDSilane), 1,3-diisobutyl-1,1,3,3-tetramethyldisilazane, 1,1,3,3-tetramethyldisilazane (TMDS), n,n-dimethylamino-trimethylsilane (TMSDMA), n,n-diethylaminotrimethylsilane (TMSDEA), hexamethyldisilazane (HMDS), heptamethyldisilazane(HeptaMDS), 1,1,3,3,5,5-hexamethylcyclotrisilazane (HMCTS), bis(dimethylamino)dimethylsilane (BIDMAIDS), bis(dimethylamino)methylsilane (B[DMA]MS)and mixtures thereof.

Claim 5

The process of claim 1, wherein said step of exposing comprises the steps of: entraining a vapor of said organometallic compound in a carrier gas; and introducing the entrained organometallic vapor into a chamber containing the workpiece.

Claim 6

The process of claim 1, wherein said step of exposing comprises contacting liquid organometallic compound with the upper surface of the first layer.

Claim 7

The process of claim 1, wherein said first layer comprises an organic polymer having bonding site for metal atoms.

Claim 8

The process of claim 6, wherein said bonding sites for the metal atoms are hydroxyl groups.

Claim 9

The process of claim 6, wherein said organic polymer comprises Novolak resin.

Claim 10

The process of claim 1, wherein the workpiece has a topographical relief between a lowest point and a highest point of the workpiece surface, and wherein said first layer is of sufficiently thickness that the upper surface thereof is substantially planar and wherein said metallizing of the upper portion of the first layer is such that a thickness of said unmetallized lower portion of said first layer exceeds said relief.

Claim 11

The process of claim 1, wherein said preselected wavelength is the I-line of ultraviolet light (365 nm).

Claim 12

The process of claim 1, wherein said preselected wavelength is the G-line of ultraviolet light (436 nm).

Claim 13

The process of claim 1, wherein said preselected wavelength is about 248 nm.

Claim 14

A process for creating a mask on the surface of an integrated circuit workpiece, comprising the steps of: applying a first layer of resist to the surface of the workpiece, said first layer containing essentially no photoactive compound; exposing an upper surface of the first layer to an organometallic compound; responsive to said step of exposing, metallizing an upper portion of the first layer, a lower portion of the first layer remote from the upper surface left unmetallized; applying a second layer of resist to the upper surface of the first layer, the second layer being photosensitive to at least one preselected wavelength of light; selectively exposing the second layer to the preselected wavelength; developing the selectively exposed second layer to create orifices in the second layer and uncover respective areas of the metallized upper portion of the first layer; using the developed second layer as a mask, etching the respective areas of the metallized upper portion of the fist layer using an etchant which removes said metallized upper portion but does not remove said unmetallized lower portion to expose respective areas of the lower portion of the first layer; and using the etched metallized upper portion as a mask, etching lower portion of the first layer to expose respective portions of the surface of the workpiece.

Claim 15

A process for creating a mask on the surface of an integrated circuit workpiece, comprising the steps of: applying a first layer of resist to the surface of the workpiece, said first layer containing essentially no photoactive compound; exposing an upper surface of the first layer to an organometallic compound; responsive to said step of exposing, metallizing an upper portion of the first layer, a lower portion of the first layer remote from the upper surface left unmetallized; applying a second layer of resist to the upper surface of the first layer, the second layer being photosensitive to at least one preselected wavelength of light; selectively exposing the second layer to the preselected wavelength; developing the selectively exposed second layer to create orifices in the second layer and uncover respective areas of the metallized upper portion of the first layer; using the developed second layer as a mask, etching the respective areas of the metallized upper portion of the fist layer using an etchant which removes said metallized upper portion but does not remove said unmetallized lower portion to expose respective areas of the lower portion of the first layer; and using the etched metallized upper portion as a mask, etching lower portion of the first layer to expose respective portions of the surface of the workpiece.

Claim 16

A process for fabricating an integrated circuit at the surface of an integrated circuit workpiece, comprising the steps of: applying a first layer of resist capable of silylation to the surface of the workpiece; exposing an upper surface of the first layer to an organosilicon compound; responsive to said step of exposing, silylating an upper portion of the first layer, a lower portion of the first layer remote from the upper surface left unsilylated; applying a second layer of resist to the upper surface of the first layer, the second layer being photosensitive to at least one preselected wavelength of light; selectively exposing the second layer to the preselected wavelength; developing the selectively exposed second layer to create a pattern including orifices in the second layer and uncover respective areas of the silylated upper portion of the first layer; using the developed second layer as a mask, etching the respective areas of said silylated upper portion of the first layer using an etchant which preferentially etches said silylated upper portion in comparison with said unsilylated lower portion of said first layer, to expose respective areas of said lower portion of said first layer; using the etched silylated upper portion as a mask, etching lower portion of the first layer to expose respective portions of the surface of the workpiece to create an integrated circuit process mask.

Claim 17

A process for fabricating an integrated circuit at the surface of an integrated circuit workpiece, comprising the steps of: applying a first layer of resist capable of silylation to the surface of the workpiece; exposing an upper surface of the first layer to an organosilicon compound; responsive to said step of exposing, silylating an upper portion of the first layer, a lower portion of the first layer remote from the upper surface left unsilylated; applying a second layer of resist to the upper surface of the first layer, the second layer being photosensitive to at least one preselected wavelength of light; selectively exposing the second layer to the preselected wavelength; developing the selectively exposed second layer to create a pattern including orifices in the second layer and uncover respective areas of the silylated upper portion of the first layer; using the developed second layer as a mask, etching the respective areas of said silylated upper portion of the first layer using an etchant which preferentially etches said silylated upper portion in comparison with said unsilylated lower portion of said first layer, to expose respective areas of said lower portion of said first layer; using the etched silylated upper portion as a mask, etching lower portion of the first layer to expose respective portions of the surface of the workpiece to create an integrated circuit process mask.

Claim 18

The process of claim 14, wherein said steps further comprise implanting a dopant into the exposed portions of the integrated circuit workpiece.

Claim 19

The process of claim 14, wherein said steps further comprise forming a layer of material on the integrated circuit workpiece surface with said exposed respective portions thereof.

Claim 20

The process of claim 14, wherein said steps further comprise etching the integrated circuit workpiece surface within said respective exposed portions thereof.