US5319768A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Control circuit for resetting a snoop valid bit in a dual port cache tag memory
Assignee: STMicroelectronics lnc USA
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Filing: 1991-05-01
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Granted: 1994-06-07
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Expires: 2011-05-01
Abstract
Abstract A control circuit for a dual port cache tag memory is used to reset a snoop valid bit for an entry addressed through one of the dual ports. This port snoops a main memory bus, and a cache tag hit which occurs during a write operation to the main memory bus indicates that the snoop valid bit for the addressed entry should be reset. In order to avoid errors in resetting the snoop valid bit, which errors can occur due to signal propagation delay, the control circuit resets the snoop valid bit only after a preselected internal delay period.
Inventors
- 👤 Bahador Rastegar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:32
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
193 words
A cache tag memory device having a dual port memory array, the array having a plurality of entries, each having a tag portion and a snoop valid bit, the memory further having a first port for addressing a first array entry and a first comparator for comparing the first array entry with a portion of a first port address, and having a second port for addressing a second array entry and a second comparator for comparing the second array entry with a portion of a second port address, the cache tag memory device further comprising: means for writing a snoop invalid value into the snoop valid bit for the second array entry addressed by the second port in response to a match signal generated by the second comparator during a write operation; and means for delaying receipt of the match signal by the means for writing for a period of time at least as great as an expected worst case delay of all signals affecting the generation of the match signal so that the means for writing is enabled only during a system bus write cycle in which a cache hit is generated.
Claim 2
Dependent Claim
193 words
A cache tag memory device having a dual port memory array, the array having a plurality of entries, each having a tag portion and a snoop valid bit, the memory further having a first port for addressing a first array entry and a first comparator for comparing the first array entry with a portion of a first port address, and having a second port for addressing a second array entry and a second comparator for comparing the second array entry with a portion of a second port address, the cache tag memory device further comprising: means for writing a snoop invalid value into the snoop valid bit for the second array entry addressed by the second port in response to a match signal generated by the second comparator during a write operation; and means for delaying receipt of the match signal by the means for writing for a period of time at least as great as an expected worst case delay of all signals affecting the generation of the match signal so that the means for writing is enabled only during a system bus write cycle in which a cache hit is generated.
Claim 3
Dependent Claim
190 words
A control circuit for a dual port memory having a plurality of memory entries, each entry including a snoop valid bit, the control circuit comprising: comparator means for detecting a match between one of said memory entries and an address on a system bus, and generating a match signal when a match is detected; a buffer for writing a first preselected value to the snoop valid bit of said one of said memory entries, the buffer having a control input for enabling the buffer to write to the snoop valid bit of said one of said memory entries; means for providing a delayed control signal to the control input of the buffer to enable the buffer in response to the match signal, wherein the control signal indicates that a write operation is taking place on the system bus and is delayed by a period of time at least as great as an expected worst case delay of all signals affecting the generation of the match signal by the comparator means so that the buffer is enabled only during a system bus write cycle in which a match signal is generated.
Claim 4
Dependent Claim
190 words
A control circuit for a dual port memory having a plurality of memory entries, each entry including a snoop valid bit, the control circuit comprising: comparator means for detecting a match between one of said memory entries and an address on a system bus, and generating a match signal when a match is detected; a buffer for writing a first preselected value to the snoop valid bit of said one of said memory entries, the buffer having a control input for enabling the buffer to write to the snoop valid bit of said one of said memory entries; means for providing a delayed control signal to the control input of the buffer to enable the buffer in response to the match signal, wherein the control signal indicates that a write operation is taking place on the system bus and is delayed by a period of time at least as great as an expected worst case delay of all signals affecting the generation of the match signal by the comparator means so that the buffer is enabled only during a system bus write cycle in which a match signal is generated.
Claim 5
Dependent Claim
67 words
The control circuit of claim 2, wherein the means for providing a delayed control signal comprises: an AND gate having an output connected to the control input of the buffer, a first input for receiving the match signal, and a second input; and a delay circuit having an input for receiving the control signal and having an output connected to the second input of the AND gate.
Claim 6
Dependent Claim
22 words
The control circuit of claim 3, wherein the delay circuit comprises a plurality of inverters connected to form an inverter delay chain.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-06 | 1997-12-06 | 1998-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-06 | 2001-12-06 | 2002-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-06 | 2005-12-06 | 2006-06-07 | $7700.00 | Window Closed / Lapsed |