Semiconductor memory unit utilizing a security code generator for selectively inhibiting memory access

Claim 2

A semiconductor memory block connectable to an information processing apparatus, said semiconductor memory block comprising: memory means for storing information; access means including an address bus, a control bus, and a data bus for accessing said memory means; security code generation means for generating a predetermined security code; collation means for comparing the predetermined security code generated by said security code generation means with an address signal on the address bus supplied by said information processing apparatus and generating an output signal when the security code coincides with the address signal; and control bus changeover means for placing said semiconductor memory block in a pseudo access mode by connecting the control bus to said collation means, thereby preventing the information processing apparatus from accessing said memory means whenever said semiconductor memory block is connected to the information processing apparatus and thereafter supplied with electrical power, and for placing the semiconductor memory block in a normal access mode by connecting said control bus to said memory means, thereby giving the information processing apparatus repeated access to said memory means without operation of said collation means whenever said collation means generates an output signal indicating that the predetermined security code coincides with the address signal supplied by the information processing apparatus and said semiconductor memory block is in the pseudo access mode.

Claim 3

The semiconductor memory block of claim 1 comprising pseudo access mode inhibition means for counting a number of times that the information processing apparatus accesses said semiconductor memory block while said semiconductor memory block is in the pseudo access mode and for inhibiting access by the information processing apparatus to said semiconductor memory block after a predetermined number of times is counted.

Claim 4

The semiconductor memory block including a plurality of memory blocks according to claim 1 connected in parallel, said memory blocks having security functions which are effective independently wherein said security code generation means of each of said memory blocks respectively generates a different predetermined security code; and memory block selection means for making at least one of said plurality of memory blocks accessible in the pseudo access mode in accordance with an upper address signal on the address bus.

Claim 5

The semiconductor memory block according to claim 2 wherein said semiconductor memory block is a memory card.

Claim 6

The semiconductor memory block according to claim 2 wherein the pseudo access inhibition means is a non-volatile memory device.

Claim 7

The semiconductor memory block according to claim 3 wherein each of said memory blocks includes pseudo access inhibition means for counting a number of times that the information processing apparatus accesses said semiconductor memory block while said semiconductor memory block is in the pseudo access mode and for inhibiting access by the information processing apparatus to said semiconductor memory block after a predetermined number of times is counted.

Claim 8

The semiconductor memory block according to claim 6 wherein the pseudo access inhibition means is a non-volatile memory device.

Claim 9

The semiconductor memory unit according to claim 6 wherein said semiconductor memory unit is a memory card.

Claim 10

An information processing system comprising: at least one semiconductor memory unit including: memory means for storing information, access means including an address bus, a control bus, and a data bus for accessing said memory means, security code generation means for generating a predetermined security code, collation means for comparing the predetermined security code generated by said security code generating means with an address signal on said address bus and generating an output signal when the security code coincides with the address signal, and control bus changeover means for placing said semiconductor memory unit in a pseudo access mode by connecting said control bus to said collation means and disconnecting said control bus from said memory means whenever said collation means generates the output indicating that the predetermined security code coincides with the address signal, thereby preventing the information processing apparatus from accessing said memory means and said semiconductor memory unit is in the pseudo access mode, and for placing said semiconductor memory unit in a normal access mode by connecting said control bus to said memory means to enable repeated access to said memory means without operation of said collation means; and at least one information processing apparatus for applying electrical power to said semiconductor memory unit, for performing automatic and manual initiation of the pseudo access mode, and for generating on the address bus said address signal coinciding with the predetermined security code.

Claim 11

An information processing system comprising: at least one semiconductor memory unit including: memory means for storing information, access means including an address bus, a control bus, and a data bus for accessing said memory means, security code generation means for generating a predetermined security code, collation means for comparing the predetermined security code generated by said security code generating means with an address signal on said address bus and generating an output signal when the security code coincides with the address signal, and control bus changeover means for placing said semiconductor memory unit in a pseudo access mode by connecting said control bus to said collation means and disconnecting said control bus from said memory means whenever said collation means generates the output indicating that the predetermined security code coincides with the address signal, thereby preventing the information processing apparatus from accessing said memory means and said semiconductor memory unit is in the pseudo access mode, and for placing said semiconductor memory unit in a normal access mode by connecting said control bus to said memory means to enable repeated access to said memory means without operation of said collation means; and at least one information processing apparatus for applying electrical power to said semiconductor memory unit, for performing automatic and manual initiation of the pseudo access mode, and for generating on the address bus said address signal coinciding with the predetermined security code.

Claim 12

The information processing system according to claim 9 including a pseudo access inhibition means for counting a number of times that the information processing apparatus accesses said semiconductor memory unit while said semiconductor memory unit is in the pseudo access mode and for inhibiting access by the information processing apparatus to said semiconductor memory unit after a predetermined number of times is counted.

Claim 13

The information processing system according to claim 10 wherein the pseudo access inhibition means is a non-volatile memory device.