Device with host indication combination

Claim 3

The device of claim 1, wherein the device is coupled to a host system and further comprising means for transferring the data blocks includes: control means, coupled to the means for generating the first signal, for generating an interrupt signal responsive to the first signal and for supplying status information concerning the first and second data blocks which may be sued by the host system.

Claim 4

The device of claim 2, wherein the status information includes the first signal and the second signal.

Claim 5

The device of claim 1, wherein the means for generating the second signal includes: a counter, having a counter output and coupled to the buffer memory, for counting the amount of data received by the buffer memory; a first alterable storage location containing a ready threshold value; means for comparing the counter output to the ready threshold value in the first alterable storage location and generating the second signal responsive to a comparison of the counter output and the ready threshold value.

Claim 6

The device of claim 4, wherein the means for delaying the first signal includes: a second alterable storage location containing a transfer complete delay threshold value; an adder, having an adder output and coupled to the counter and the second alterable storage location, for outputting the sum of the values of the counter output and the transfer complete delay threshold value; and a comparator, coupled to the adder output and the first alterable storage location, for indicating the expected occurrence of the second signal responsive to a comparison of the adder output and the ready threshold value.

Claim 9

The apparatus of claim 6, wherein the network interface logic waits an interframe spacing time interval between transferring successive data frames and the period of time occurs during the inter-frame spacing time interval.

Claim 10

The apparatus of claim 6, wherein the host interface logic includes: transfer descriptor logic for mapping transfer descriptors from the host system to the buffer memory, the transfer descriptors identifying locations in host memory to which a data frame in the buffer memory is to be stored; and upload logic, responsive to transfer descriptors in the buffer memory, for transferring a data frame from the buffer memory to host memory.

Claim 11

The apparatus of claim 6, wherein the host interface logic includes: control means for generating an interrupt signal to the host system responsive to the transfer complete indication signal and for supplying status information which may be used by the host system.

Claim 12

The apparatus of claim 6, wherein the host system includes host address space, and the buffer memory comprises a buffer independent of the host address space.

Claim 13

The apparatus of claim 6, wherein the receive threshold logic includes: a counter, having a counter output and coupled to the buffer memory, for counting the portion of the data frame transferred to the buffer memory from the network transceiver; a first alterable storage location containing a receive threshold value; means for comparing the counter output to the receive threshold value in the first alterable storage location and generating an early receive indication signal responsive to a comparison of the counter output and the receive threshold value.

Claim 14

The apparatus of claim 11, wherein the data frame includes a header field, including a destination address, followed by a data field and the receive threshold value is a look-ahead threshold value representing an amount of data relative to the beginning of the header field.

Claim 15

The apparatus of claim 12, wherein the network interface logic transfers the destination address from the network transceiver to the buffer memory during the period of time.

Claim 16

The apparatus of claim 12, wherein the network interface logic transfers the look-ahead threshold amount of data from the network transceiver to the buffer memory during the period of time.

Claim 17

The apparatus of claim 11, wherein the indication combination logic includes: a second alterable storage location containing a transfer complete delay threshold value; an adder, having an adder output coupled to the counter and the second alterable storage location, for outputting the sum of the values of the counter output and the transfer complete delay threshold value; and a comparator, coupled to the adder output and the first alterable storage location, for indicating an end of the period of time responsive to a comparison of the adder output and the look-ahead threshold value.

Claim 20

The apparatus of claim 16, wherein the receive threshold logic includes: a counter, having a counter output and coupled to the buffer memory, for counting the portion of the data frame transferred to the buffer memory from the network communication media; a first alterable storage location containing a receive threshold value; and means for comparing the counter output to the receive threshold value in the first alterable storage location and generating an indication signal responsive to a comparison to the counter output and the receive threshold value.

Claim 21

The apparatus of claim 17, wherein the data frame includes a header field, including a destination address, followed by a data field and the receive threshold value is a look-ahead threshold value representing an amount of data relative to the beginning of the header field.

Claim 22

The apparatus of claim 18, wherein there is an inter-frame spacing time interval between data frames transferred by the network interface logic and the period of time is during the inter-frame spacing time.

Claim 23

The apparatus of claim 18, the network interface logic transfers the destination address from the network transceiver to the buffer during the period of time.

Claim 24

The apparatus of claim 18, wherein the network interface logic transfers the look-ahead threshold amount of data from the network transceiver to the buffer during the period of time.

Claim 25

The apparatus of claim 17, wherein the indication combination logic includes: a second alterable storage location containing a transfer complete delay threshold value; an adder, having an adder output and coupled to the counter and the second alterable storage location, for outputting the sum of the values of the counter output and the transfer complete delay threshold value; and a comparator, coupled to the adder output and the first alterable storage location, for indicating an end of the period of time responsive to a comparison of the adder output and the look-ahead threshold value.

Claim 26

A network adapter, having a buffer memory, for transferring a data frame from a network transceiver, coupled with a network, to the buffer memory and transferring a data frame from the buffer memory to a host system including a host processor and host memory, the network adapter generating an interrupt signal to the host processor responsive to transferring a data frame, the host processor responding to the interrupt signal and servicing the network adapter during a period of time, the network adapter comprising: network interface logic, coupled to the buffer memory and the network transceiver, for transferring a data frame from the network transceiver to the buffer memory; receive threshold logic, coupled to the buffer memory and the network interface logic, for generating an early receive indication signal responsive to transferring the data frame from the network transceiver to the buffer memory, wherein the receive threshold logic includes: a counter, having a counter output and coupled to the buffer memory, for counting a portion of the data frame transferred to the buffer memory from the network transceiver; a first alterable storage location containing a receive threshold value; and, means for comparing the counter output to the receive threshold value in the first alterable storage location and generating an indication signal responsive to a comparison to the counter output and the receive threshold value; host interface logic, coupled to the buffer memory and the host system, for transferring a data frame from the buffer memory to the host system; transfer complete logic, coupled to the host interface logic, for generating a transfer complete indication signal responsive to transferring a data frame to the host system; control means, coupled to the host interface logic, for generating an interrupt signal to the host processor responsive to the transfer complete indication signal and posting status information representing the early receive indication signal and transfer complete indication signal which may be read by the host processor; and indication combination logic, coupled to the receive threshold logic and the transfer complete logic, for delaying the transfer complete indication signal such that the early receive indication occurs during the period of time the host processor is servicing the network adapter.

Claim 27

A network adapter, having a buffer memory, for transferring a data frame from a network transceiver, coupled with a network, to the buffer memory and transferring a data frame from the buffer memory to a host system including a host processor and host memory, the network adapter generating an interrupt signal to the host processor responsive to transferring a data frame, the host processor responding to the interrupt signal and servicing the network adapter during a period of time, the network adapter comprising: network interface logic, coupled to the buffer memory and the network transceiver, for transferring a data frame from the network transceiver to the buffer memory; receive threshold logic, coupled to the buffer memory and the network interface logic, for generating an early receive indication signal responsive to transferring the data frame from the network transceiver to the buffer memory, wherein the receive threshold logic includes: a counter, having a counter output and coupled to the buffer memory, for counting a portion of the data frame transferred to the buffer memory from the network transceiver; a first alterable storage location containing a receive threshold value; and, means for comparing the counter output to the receive threshold value in the first alterable storage location and generating an indication signal responsive to a comparison to the counter output and the receive threshold value; host interface logic, coupled to the buffer memory and the host system, for transferring a data frame from the buffer memory to the host system; transfer complete logic, coupled to the host interface logic, for generating a transfer complete indication signal responsive to transferring a data frame to the host system; control means, coupled to the host interface logic, for generating an interrupt signal to the host processor responsive to the transfer complete indication signal and posting status information representing the early receive indication signal and transfer complete indication signal which may be read by the host processor; and indication combination logic, coupled to the receive threshold logic and the transfer complete logic, for delaying the transfer complete indication signal such that the early receive indication occurs during the period of time the host processor is servicing the network adapter.

Claim 28

The network adapter of claim 23, wherein the data frame includes a header field, including a destination address, followed by a data field and the receive threshold value is a look-ahead threshold value representing an amount of data relative to the beginning of the header field.

Claim 29

The network adapter of claim 24, wherein the transfer complete indication signal is generated after the destination address is transferred from the network transceiver to the buffer memory.

Claim 30

The network adapter of claim 25, wherein the transfer complete indication signal is generated before the look-ahead threshold value of data is transferred from the network transceiver to the buffer memory.

Claim 31

The network adapter of claim 24, wherein the indication combination logic includes: a second alterable storage location containing a transfer complete delay threshold value; an adder, having an adder output and coupled to the counter and the second alterable storage location, for outputting the sum of the values of the counter output and the transfer complete delay threshold value; and a comparator, coupled to the adder output and the first alterable storage location, for indicating the expected occurrence of the early receive indication signal responsive to a comparison of the adder output and the look-ahead threshold value.

Claim 32

The network adapter of claim 23, wherein the transfer complete indication signal is generated after the portion of the data frame is transferred from the network transceiver to the buffer memory.