Active filter circuit

Claim 2

An active filter circuit, comprising: a first differential pair constructed to include first and second transistors; a first capacitive load connected to a collector of said second transistor of said first differential pair; a first negative feed-back transistor for feeding-back an output at said collector of said second transistor to a base of said second transistor; a second differential pair constructed to include third and fourth transistors; a second capacitive load connected to a collector of said fourth transistor of said second differential pair; a second negative feed-back transistor for feeding-back an output at said collector of said fourth transistor to a base of said first transistor constituting said first differential pair; fifth and sixth transistors for forming a first current mirror circuit which is connected to said collector of said second transistor; seventh and eighth transistors for forming a second current mirror circuit which is connected to said collector of said fourth transistor; and biasing means formed in association with at least one of said first and second differential pairs for applying bias voltage to bases of two transistors constituting said at least one of the differential pairs, said biasing means including resistor voltage-dividing means for applying a divided voltage to respective bases of said two transistors as said bias voltages.

Claim 3

An active filter circuit, comprising: a first differential pair constructed to include first and second transistors; a first capacitive load connected to a collector of said second transistor of said first differential pair; a second differential pair constructed to include third and fourth transistors; a fifth transistor for supplying an output at said collector of said second transistor of said first differential pair to a base of said fourth transistor of said second differential pair; a second capacitive load connected to said collector of said fourth transistor; a negative feed-back transistor for feeding-back an output at said collector of said fourth transistor to a base of said first transistor constituting said first differential pair; sixth and seventh transistors for forming a first current mirror circuit which is connected to said collector of said second transistor; eighth and ninth transistors for forming a current mirror circuit which is connected to said collector of said fourth transistor; and biasing means formed in association with at least one of said first and second differential pairs for applying bias voltages to bases of two transistors constituting said at least one of the differential pairs, said biasing means including resistor voltage-dividing means for applying a divided voltage to respective bases of said two transistors as said bias voltages.

Claim 4

An active filter circuit, comprising: a first differential pair constructed to include first and second transistors; a first capacitive load connected to a collector of said second transistor of said first differential pair; a second differential pair constructed to include third and fourth transistors; a fifth transistor for supplying an output at said collector of said second transistor of said first differential pair to a base of said fourth transistor of said second differential pair; a second capacitive load connected to said collector of said fourth transistor; a negative feed-back transistor for feeding-back an output at said collector of said fourth transistor to a base of said first transistor constituting said first differential pair; sixth and seventh transistors for forming a first current mirror circuit which is connected to said collector of said second transistor; eighth and ninth transistors for forming a current mirror circuit which is connected to said collector of said fourth transistor; and biasing means formed in association with at least one of said first and second differential pairs for applying bias voltages to bases of two transistors constituting said at least one of the differential pairs, said biasing means including resistor voltage-dividing means for applying a divided voltage to respective bases of said two transistors as said bias voltages.

Claim 5

An active filter circuit in accordance with claim 1 or 2, further comprising current changing means for correlatively changing circuit amounts of said first and second differential pairs in response to a given control voltage.

Claim 6

An active filter circuit in accordance with claim 1, wherein said resistor voltage-dividing means includes a first resistor series connection having a series connecting point connected to the base of one of said two transistors, and a second resistor series connection having a series connecting point connected to the base of another of said two transistors.

Claim 7

An active filter circuit in accordance with claim 4, wherein said biasing means includes a bias voltage source, and respective one ends of the two resistor series connections are connected to said bias voltage source.

Claim 8

An active filter circuit in accordance with claim 4, wherein said first and second resistor series connections include a common resistor which is interconnected between the bases of said two transistors.

Claim 9

A filter controlling circuit, comprising: a filter for receiving an input and for outputting an output with a phase characteristic, said phase characteristic of said filter changing in accordance with a control voltage; means, coupled to said filter, for outputting a direct current voltage component having a level based on said phase characteristic of said output of said filter; level comparing means for comparing said level of said direct current voltage component with a reference voltage; and means for applying said control voltage to said filter based upon an output of said level comparing means.

Claim 10

A filter controlling circuit, comprising: a filter for receiving an input and for outputting an output with a phase characteristic, said phase characteristic of said filter changing in accordance with a control voltage; means, coupled to said filter, for outputting a direct current voltage component having a level based on said phase characteristic of said output of said filter; level comparing means for comparing said level of said direct current voltage component with a reference voltage; and means for applying said control voltage to said filter based upon an output of said level comparing means.

Claim 11

A filter controlling circuit in accordance with claim 7, wherein said filter includes: a first differential pair constructed to include a first and second transistors; a first capacitive load connected to an output of said second transistor of said first differential pair; a first negative feed-back path for feeding-back an output of said second transistor to an input thereof; a second differential pair constructed to include a third and fourth transistors; a second capacitive load connected to an output of said fourth transistor of said second differential pair; a second negative feed-back path for feeding-back an output of said fourth transistor to an input of said first transistor constituting the first differential pair; and current changing means for correlatively changing current amounts of said first and second differential pairs in response to said control voltage.

Claim 12

A filter controlling circuit in accordance with claim 7, wherein said filter include: a first differential pair constructed to include a first and second transistors; a first capacitive load connected to an output of said second transistor of said first differential pair; a second differential pair constructed to include a third and fourth transistors; a connecting path for connecting an output of said second transistor of said first differential pair to an input of said fourth transistor of said second differential pair; a second capacitive load connected to an output of said fourth transistor; a negative feed-back path for feeding-back an output of said fourth transistor to an input of said first transistor constituting said first differential pair; and current changing means for correlatively changing current amounts of said first and second differential pairs in response to said control voltage.

Claim 13

A filter controlling circuit comprising: a filter, a center frequency of said filter being able to be changed in accordance with a control voltage; amplifying means having a gain of 1 or more for feeding-back an output of said filter to an input of said filter; phase comparing means receiving the output of said filter and a further input signal; and means for applying said control voltage to said filter based upon an output of said phase comparing means, wherein said filter includes, a first differential pair constructed to include first and second transistors; a first capacitive load connected to a collector of said second transistor of said first differential pair; a first negative feed-back path for feeding-back an output at said collector of said second transistor to a base of said second transistor; a second differential pair constructed to include third and fourth transistors; a second capacitive load connected to a collector of said fourth transistor of said second differential pair; a second negative feed-back path for feeding-back an output at said collector of said fourth transistor to a base of said first transistor constituting said first differential pair; current changing means for correlatively changing current amounts of said first and second differential pairs in response to said control voltage; and biasing means formed in association with at least one of said first and second differential pairs for applying bias voltages to bases of two transistors constituting said at least one of the differential pairs, said biasing means including resistor voltage-dividing means or applying a divided voltage to respective bases of said two transistors as said bias voltages.

Claim 14

A filter controlling circuit comprising: a filter, a center frequency of said filter being able to be changed in accordance with a control voltage; amplifying means having a gain of 1 or more for feeding-back an output of said filter to an input of said filter; phase comparing means receiving the output of said filter and a further input signal; and means for applying said control voltage to said filter based upon an output of said phase comparing means, wherein said filter includes, a first differential pair constructed to include first and second transistors; a first capacitive load connected to a collector of said second transistor of said first differential pair; a first negative feed-back path for feeding-back an output at said collector of said second transistor to a base of said second transistor; a second differential pair constructed to include third and fourth transistors; a second capacitive load connected to a collector of said fourth transistor of said second differential pair; a second negative feed-back path for feeding-back an output at said collector of said fourth transistor to a base of said first transistor constituting said first differential pair; current changing means for correlatively changing current amounts of said first and second differential pairs in response to said control voltage; and biasing means formed in association with at least one of said first and second differential pairs for applying bias voltages to bases of two transistors constituting said at least one of the differential pairs, said biasing means including resistor voltage-dividing means or applying a divided voltage to respective bases of said two transistors as said bias voltages.

Claim 15

A filter controlling circuit comprising: a filter, a center frequency of said filter being able to be changed in accordance with a control voltage; amplifying means having a gain of 1 or more for feeding-back an output of said filter to an input of said filter; phase comparing means receiving the output of said filter and a further input signal; and means for applying said control voltage to said filter based upon an output of said phase comparing means, wherein said filter includes, a first differential pair constructed to include first and second transistors; a first capacitive load connected to a collector of said second transistors of said first differential pair; a second differential pair constructed to include third and fourth transistors; a connecting path for connecting said collector of said second transistor of said first differential pair to a base of said fourth transistor of said second differential pair; a second capacitive load connected to said collector of said fourth transistor; a negative feed-back path for feeding-back said collector of said fourth transistor to a base of said first transistor constituting said first differential pair; current changing means for correlatively changing current amounts of said first and second differential pairs in response to said control voltage; and biasing means formed in association with at least one of said first and second differential pairs for applying bias voltages to bases of two transistors constituting said at least one of the differential pairs, said biasing means including resistor voltage-dividing means for applying a divided voltage to respective bases of said two transistors as said bias voltages.

Claim 16

A filter controlling circuit comprising: a filter, a center frequency of said filter being able to be changed in accordance with a control voltage; amplifying means having a gain of 1 or more for feeding-back an output of said filter to an input of said filter; phase comparing means receiving the output of said filter and a further input signal; and means for applying said control voltage to said filter based upon an output of said phase comparing means, wherein said filter includes, a first differential pair constructed to include first and second transistors; a first capacitive load connected to a collector of said second transistors of said first differential pair; a second differential pair constructed to include third and fourth transistors; a connecting path for connecting said collector of said second transistor of said first differential pair to a base of said fourth transistor of said second differential pair; a second capacitive load connected to said collector of said fourth transistor; a negative feed-back path for feeding-back said collector of said fourth transistor to a base of said first transistor constituting said first differential pair; current changing means for correlatively changing current amounts of said first and second differential pairs in response to said control voltage; and biasing means formed in association with at least one of said first and second differential pairs for applying bias voltages to bases of two transistors constituting said at least one of the differential pairs, said biasing means including resistor voltage-dividing means for applying a divided voltage to respective bases of said two transistors as said bias voltages.

Claim 17

A filter controlling circuit in accordance with claim 7, wherein said filter includes: a first differential pair constructed to include first and second transistors; a first capacitive load connected to an output of said second transistor of said first differential pair; a first negative feed-back path for feeding-back an output of said second transistor to an input thereof; a second differential pair constructed to include third and fourth transistors; a second capacitor load connected to an output of said fourth transistor of said second differential pair; a second negative feed-back path for feeding-back an output of said fourth transistor to an input of said first transistor constituting the first differential pair; current changing means for correlatively changing current amounts of said first and second differential pairs in response to said control voltage; and biasing means formed in association with at least one of said first and second differential pairs for applying bias voltages to bases of two transistors constituting said at least one of the differential pairs, said biasing means including resistor voltage-dividing means for applying a divided voltage to respective bases of said two transistors as said bias voltages.

Claim 18

A filter controlling circuit in accordance with claim 7, wherein said filter includes: a first differential pair constructed to include first and second transistors; a first capacitive load connected to an output of said second transistor of said first differential pair; a second differential pair constructed to include third and fourth transistors; a connecting path for connecting an output of said second transistor of said first differential pair to an input of said fourth transistor of said second differential pair; a second capacitive load connected to an output of said fourth transistor; a negative feed-back path for feeding-back an output of said fourth transistor to an input of said first transistor constituting said first differential pair; current changing means for correlatively changing current amounts of said first and second differential pairs in response to said control voltage; and biasing means formed in association with at least one of said first and second differential pairs for applying bias voltages to bases of two transistors constituting said at least one of the differential pairs, said biasing means including resistor voltage-dividing means for applying a divided voltage to respective bases of said two transistors as said bias voltage.

Claim 19

An active filter circuit in accordance with claim 2, wherein said resistor voltage-dividing means includes a first resistor series connection having a series connecting point connected to the base of one of said two transistors, and a second resistor series connection having a series connecting point connected to the base of another of said two transistors.

Claim 20

An active filter circuit, comprising: a first differential pair constructed to include first and second transistors; a first capacitive load connected to a collector of said second transistor of said first differential pair; a first negative feed-back transistor for feeding-back an output at said collector of said second transistor to a base of said second transistor; a second differential pair constructed to include third and fourth transistors; a second capacitive load connected to a collector of said fourth transistor of said second differential pair; a second negative feed-back transistor for feeding-back an output at said collector of said fourth transistor to a base of said first transistor constituting said first differential pair; fifth and sixth transistors for forming a first current mirror circuit which is connected to said collector of said second transistor; and seventh and eighth transistors for forming a second current mirror circuit which is connected to said collector of said fourth transistor.

Claim 21

An active filter circuit, comprising: a first differential pair constructed to include first and second transistors; a first capacitive load connected to a collector of said second transistor of said first differential pair; a first negative feed-back transistor for feeding-back an output at said collector of said second transistor to a base of said second transistor; a second differential pair constructed to include third and fourth transistors; a second capacitive load connected to a collector of said fourth transistor of said second differential pair; a second negative feed-back transistor for feeding-back an output at said collector of said fourth transistor to a base of said first transistor constituting said first differential pair; fifth and sixth transistors for forming a first current mirror circuit which is connected to said collector of said second transistor; and seventh and eighth transistors for forming a second current mirror circuit which is connected to said collector of said fourth transistor.

Claim 22

An active filter circuit according to claim 15, further comprising a third current mirror circuit for determining currents of said first current mirror circuit, said second current mirror circuit, said first differential pair and said second differential pair.

Claim 23

An active filter circuit according to claim 16, further comprising a terminal for inputting a control signal, a current of said third current mirror circuit being controlled by said control signal such that a filter characteristic of said active filter can be changed.

Claim 24

An active filter circuit, comprising: a first differential pair constructed to include first and second transistors; a first capacitive load connected to a collector of said second transistor of said first differential pair; a second differential pair constructed to include third and fourth transistors; a fifth transistor for supplying an output at said collector of said second transistor of said first differential pair to a base of said fourth transistor of said second differential pair; a second capacitive load connected to a collector of said fourth transistor; a negative feed-back transistor for feeding-back an output at said collector of said fourth transistor to a base of said first transistor constituting said first differential pair; sixth and seventh transistors for forming a current mirror circuit which is connected to said collector of said second transistor; and eighth and ninth transistors for forming a current mirror circuit which is connected to said collector of said fourth transistor.

Claim 25

An active filter circuit, comprising: a first differential pair constructed to include first and second transistors; a first capacitive load connected to a collector of said second transistor of said first differential pair; a second differential pair constructed to include third and fourth transistors; a fifth transistor for supplying an output at said collector of said second transistor of said first differential pair to a base of said fourth transistor of said second differential pair; a second capacitive load connected to a collector of said fourth transistor; a negative feed-back transistor for feeding-back an output at said collector of said fourth transistor to a base of said first transistor constituting said first differential pair; sixth and seventh transistors for forming a current mirror circuit which is connected to said collector of said second transistor; and eighth and ninth transistors for forming a current mirror circuit which is connected to said collector of said fourth transistor.

Claim 26

An active filter circuit according to claim 18, further comprising a third current mirror circuit for determining currents of said first current mirror circuit, said second current mirror circuit, said first differential pair and said second differential pair.

Claim 27

An active filter circuit according to claim 19, further comprising a terminal for inputting a control signal, a current of said third mirror circuit being controlled by said control signal such that a filter characteristic of said active filter circuit can be changed.

Claim 28

A filter controlling circuit as claimed in claim 7 wherein said means for outputting a direct current voltage component includes a multiplier and a low-pass filter.