US5315284A
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Asynchronous digital threshold detector for a digital data storage channel
Assignee: International Business Machines Corp
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Filing: 1993-06-07
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Granted: 1994-05-24
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Expires: 2013-06-07
Abstract
Abstract A zero-crossing detector for asynchronous detection of threshold transitions in a digitally sampled signal waveform. The Asynchronous Digital Threshold Detector (ADTD) receives a digitized self-clocking data readback waveform and provides the relative location of a zero-crossing within the sample period where it occurs. The digital output, which is useful for recovering data and clock signals, is in a digital form that can be used directly by a certain class of asynchronous digital phase detector systems. The ADTD is entirely digital and can be embodied in a low power configuration using CMOS technology.
Inventors
- 👤 Steven R. Bentley
- 👤 Robert A. Hutchins
- 👤 Constantin M. Melas
- 👤 Pantas Sutardja
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:18
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/153; H03K5/1536; G; G11; G11B; G11B20/00; G11B20/10; G11B20/10009
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
258 words
A method for asynchronous detection of the time t of a threshold transition in a signal waveform having a data clock rate F d , said method comprising the steps of: (a) sampling said signal waveform at a first clock rate R s =2F d equal to the reciprocal of a first sampling interval T s to create a plurality of digital sample signals {S} representing a series of instantaneous values of said signal waveform including an i th sample signal S i and the preceding adjacent sample signal S i-1 where i is a nonzero positive integer; (b) creating a detection signal responsive to a signal difference between said sample signal S i and said sample signal S i-1 ; (c) doubling said first sampling interval T s to create a second sampling interval T d =2T s equal to the reciprocal of said data clock rate F d ; (d) creating a first digital signal corresponding to that half of said second sampling interval T d in which said detection signal is located; (e) creating a second digital signal by interpolating between said sample signal S i and said sample signal S i-1 , wherein said second digital signal represents an estimate of the location t/T s of said threshold transition within an i th said first sampling interval T s ; and (f) combining said first and second digital signals to create a third digital signal representing the location t/T d of said threshold transition within a contemporaneous said second sampling interval T d .
Claim 2
Independent Claim
258 words
A method for asynchronous detection of the time t of a threshold transition in a signal waveform having a data clock rate F d , said method comprising the steps of: (a) sampling said signal waveform at a first clock rate R s =2F d equal to the reciprocal of a first sampling interval T s to create a plurality of digital sample signals {S} representing a series of instantaneous values of said signal waveform including an i th sample signal S i and the preceding adjacent sample signal S i-1 where i is a nonzero positive integer; (b) creating a detection signal responsive to a signal difference between said sample signal S i and said sample signal S i-1 ; (c) doubling said first sampling interval T s to create a second sampling interval T d =2T s equal to the reciprocal of said data clock rate F d ; (d) creating a first digital signal corresponding to that half of said second sampling interval T d in which said detection signal is located; (e) creating a second digital signal by interpolating between said sample signal S i and said sample signal S i-1 , wherein said second digital signal represents an estimate of the location t/T s of said threshold transition within an i th said first sampling interval T s ; and (f) combining said first and second digital signals to create a third digital signal representing the location t/T d of said threshold transition within a contemporaneous said second sampling interval T d .
Claim 3
Dependent Claim
21 words
The method of claim 1 wherein: said first digital signal is the Most Significant Bit (MSB) of said third digital signal.
Claim 4
Dependent Claim
122 words
The method of claim 1 wherein said creating step (e) comprises the steps of: (e.1) subtracting said sample signal S i from said sample signal S i-1 to create a denominator signal D i =S i-1 -S i ; (e.2) creating a reciprocal difference signal R i =1D i representative of the reciprocal of said denominator signal D i ; (e.3) multiplying said sample signal S i-1 and said reciprocal difference signal R i to obtain an interpolation signal R i S i-1 ; and (e.4) creating said second digital signal |R i S i-1 | by discarding the sign from said interpolation signal R i S i-1 , thereby estimating said threshold transition location t/T d =|R i S i-1 |.
Claim 5
Dependent Claim
195 words
An Asynchronous Digital Threshold Detector (ADTD) for detecting the time t of a threshold transition in a signal waveform having a data clock rate F d , said ADTD comprising: input means for accepting a plurality of digital sample signals {S} at a transfer rate F s =2F d representing a sequence of instantaneous values of said signal waveform; transition detection means coupled to said input means for assembling an adjacent pair of said digital sample signals (S i , S i-1 ) and creating a detection flag DF i responsive to a sign difference between said adjacent pair of digital sample signals (S i , S i-1 ); decimation means coupled to said transition detection means for reducing said transfer rate F s of said sample signals from 2F d to said data clock rate F d ; and time generator means coupled to said decimation means for interpolating said threshold transition time t within an interval T d equal to the reciprocal of said data clock rate F d and for creating a digital signal representative of the ratio t/T d of said threshold transition time t to said interval T d .
Claim 6
Dependent Claim
195 words
An Asynchronous Digital Threshold Detector (ADTD) for detecting the time t of a threshold transition in a signal waveform having a data clock rate F d , said ADTD comprising: input means for accepting a plurality of digital sample signals {S} at a transfer rate F s =2F d representing a sequence of instantaneous values of said signal waveform; transition detection means coupled to said input means for assembling an adjacent pair of said digital sample signals (S i , S i-1 ) and creating a detection flag DF i responsive to a sign difference between said adjacent pair of digital sample signals (S i , S i-1 ); decimation means coupled to said transition detection means for reducing said transfer rate F s of said sample signals from 2F d to said data clock rate F d ; and time generator means coupled to said decimation means for interpolating said threshold transition time t within an interval T d equal to the reciprocal of said data clock rate F d and for creating a digital signal representative of the ratio t/T d of said threshold transition time t to said interval T d .
Claim 7
Dependent Claim
33 words
The ADTD of claim 4 wherein said input means further comprises: means for accepting a pulse qualification flag representing that said threshold transition results from a signal pulse rather than a noise pulse.
Claim 8
Dependent Claim
129 words
The ADTD of claim 5 wherein said transition detection means comprises: first register means for storing the earlier said digital sample signal S i-1 of said adjacent pair of digital sample signals (S i , S i-1 ); second register means for storing the later said digital sample signal S i of said adjacent pair of digital sample signals (S i , S i-1 ); sign comparator means for creating a signal corresponding to the logical exclusive-or of the signs of said adjacent pair of digital sample signals (S i , S i-1 ); and detection qualification means for enabling the output from said sign comparator means responsive to both said pulse qualification flags corresponding to said adjacent pair of digital sample signals (S i , S i-1 ).
Claim 9
Dependent Claim
134 words
The ADTD of claim 6 wherein said decimation means comprises: third register means for storing said adjacent pair of digital sample signals (S i , S i-1 ); selection means for selecting within one said interval T d either a first said adjacent pair of digital sample signals (S i , S i-1 ) or a second said adjacent pair of digital sample signals (S i+1 , S i ); MSB means for identifying which of said first or second adjacent pairs of digital sample signals (S i , S i-1 ) is selected by said selection means; and dual clocking means for stepping the input of said decimation means at said transfer rate F s =2F d and for stepping the output of said decimation means at said data rate F d .
Claim 10
Dependent Claim
108 words
The ADTD of claim 7 wherein said time generator means comprises: reciprocal map means for creating a reciprocal digital signal |S i-1 -S i | -1 representing the reciprocal of the absolute value of the difference between said adjacent pair of digital sample signals (S i , S i-1 ); and multiplier means for multiplying said reciprocal digital signal |S i-1 -S i | -1 by the absolute value of said earlier digital sample signal |S i-1 | to obtain said digital signal representing the ratio t/T d =|S i-1 |.|S i-1 -S i | -1 of said threshold transition time t to said interval T d .
Claim 11
Dependent Claim
129 words
The ADTD of claim 4 wherein said transition detection means comprises: first register means for storing the earlier said digital sample signal S i-1 of said adjacent pair of digital sample signals (S i , S i-1 ); second register means for storing the later said digital sample signal S i of said adjacent pair of digital sample signals (S i , S i-1 ); sign comparator means for creating a signal corresponding to the logical exclusive-or of the signs of said adjacent pair of digital sample signals (S i , S i-1 ); and detection qualification means for enabling the output from said sign comparator means responsive to both said pulse qualification flags corresponding to said adjacent pair of digital sample signals (S i , S i-1 ).
Claim 12
Dependent Claim
134 words
The ADTD of claim 4 wherein said decimation means comprises: third register means for storing said adjacent pair of digital sample signals (S i , S i-1 ); selection means for selecting within one said interval T d either a first said adjacent pair of digital sample signals (S i , S i-1 ) or a second said adjacent pair of digital sample signals (S i+1 , S i ); MSB means for identifying which of said first or second adjacent pairs of digital sample signals (S i , S i-1 ) is selected by said selection means; and dual clocking means for stepping the input of said decimation means at said transfer rate F s =2F d and for stepping the output of said decimation means at said data rate F d .
Claim 13
Dependent Claim
108 words
The ADTD of claim 4 wherein said time generator means comprises: reciprocal map means for creating a reciprocal digital signal |S i-1 -S i | -1 representing the reciprocal of the absolute value of the difference between said adjacent pair of digital sample signals (S i , S i-1 ); and multiplier means for multiplying said reciprocal digital signal |S i-1 -S i | -1 by the absolute value of said earlier digital sample signal |S i-1 | to obtain said digital signal representing the ratio t/T d =|S i-1 |.|S i-1 -S i | -1 of said threshold transition time t to said interval T d .
Claim 14
Dependent Claim
239 words
In a Direct Access Storage Device (DASD) magnetic recording channel wherein digital data stored as a series of signal transitions in said DASD are read by sensing said transitions to create a signal waveform having a data clock rate F d equal to the reciprocal of a data clock interval T d and having transitions through a first threshold, said data being recovered in said channel, an Asynchronous Digital Threshold Detector (ADTD) comprising: input means for accepting a plurality of digital sample signals {S} at a transfer rate F s =2F d representing a sequence of instantaneous values of said signal waveform; transition detection means coupled to said input means for assembling an adjacent pair of said digital sample signals (S i , S i-1 ) and creating a detection flag DF i responsive to a sign difference between said adjacent pair of digital sample signals (S i , S i-1 ); decimation means coupled to said transition detection means for reducing said transfer rate F s of said digital sample signals from 2F d to said data clock rate F d ; and time generator means coupled to said decimation means for interpolating said threshold transition time t within an interval T d equal to the reciprocal of said data clock rate F d and for creating a digital signal representative of the ratio t/T d of said threshold transition time t to said interval T d .
Claim 15
Dependent Claim
239 words
In a Direct Access Storage Device (DASD) magnetic recording channel wherein digital data stored as a series of signal transitions in said DASD are read by sensing said transitions to create a signal waveform having a data clock rate F d equal to the reciprocal of a data clock interval T d and having transitions through a first threshold, said data being recovered in said channel, an Asynchronous Digital Threshold Detector (ADTD) comprising: input means for accepting a plurality of digital sample signals {S} at a transfer rate F s =2F d representing a sequence of instantaneous values of said signal waveform; transition detection means coupled to said input means for assembling an adjacent pair of said digital sample signals (S i , S i-1 ) and creating a detection flag DF i responsive to a sign difference between said adjacent pair of digital sample signals (S i , S i-1 ); decimation means coupled to said transition detection means for reducing said transfer rate F s of said digital sample signals from 2F d to said data clock rate F d ; and time generator means coupled to said decimation means for interpolating said threshold transition time t within an interval T d equal to the reciprocal of said data clock rate F d and for creating a digital signal representative of the ratio t/T d of said threshold transition time t to said interval T d .
Claim 16
Dependent Claim
33 words
The ADTD of claim 12 wherein said input means further comprises: means for accepting a pulse qualification flag representing that said threshold transition results from a signal pulse rather than a noise pulse.
Claim 17
Dependent Claim
129 words
The ADTD of claim 13 wherein said transition detection means comprises: first register means for storing the earlier said digital sample signal S i-1 of said adjacent pair of digital sample signals (S i , S i-1 ); second register means for storing the later said digital sample signal S i of said adjacent pair of digital sample signals (S i , S i-1 ); sign comparator means for creating a signal corresponding to the logical exclusive-or of the signs of said adjacent pair of digital sample signals (S i , S i-1 ); and detection qualification means for enabling the output from said sign comparator means responsive to both said pulse qualification flags corresponding to said adjacent pair of digital sample signals (S i , S i-1 ).
Claim 18
Dependent Claim
134 words
The ADTD of claim 14 wherein said decimation means comprises: third register means for storing said adjacent pair of digital sample signals (S i , S i-1 ); selection means for selecting within one said interval T d either a first said adjacent pair of digital sample signals (S i , S i-1 ) or a second said adjacent pair of digital sample signals (S i+1 , S i ); MSB means for identifying which of said first or second adjacent pairs of digital sample signals (S i , S i-1 ) is selected by said selection means; and dual clocking means for stepping the input of said decimation means at said transfer rate F s =2F d and for stepping the output of said decimation means at said data rate F d .
Claim 19
Dependent Claim
108 words
The ADTD of claim 15 wherein said time generator means comprises: reciprocal map means for creating a reciprocal digital signal |S i-1 -S i | -1 representing the reciprocal of the absolute value of the difference between said adjacent pair of digital sample signals (S i , S i-1 ); and multiplier means for multiplying said reciprocal digital signal |S i-1 -S i | -1 by the absolute value of said earlier digital sample signal |S i-1 | to obtain said digital signal representing the ratio t/T d =|S i-1 |.|S i-1 -S i | -1 of said threshold transition time t to said interval T d .
Claim 20
Dependent Claim
129 words
The ADTD of claim 12 wherein said transition detection means comprises: first register means for storing the earlier said digital sample signal S i-1 of said adjacent pair of digital sample signals (S i , S i-1 ); second register means for storing the later said digital sample signal S i of said adjacent pair of digital sample signals (S i , S i-1 ); sign comparator means for creating a signal corresponding to the logical exclusive-or of the signs of said adjacent pair of digital sample signals (S i , S i-1 ); and detection qualification means for enabling the output from said sign comparator means responsive to both said pulse qualification flags corresponding to said adjacent pair of digital sample signals (S i , S i-1 ).
Claim 21
Dependent Claim
134 words
The ADTD of claim 12 wherein said decimation means comprises: third register means for storing said adjacent pair of digital sample signals (S i , S i-1 ); selection means for selecting within one said interval T d either a first said adjacent pair of digital sample signals (S i , S i-1 ) or a second said adjacent pair of digital sample signals (S i+1 , S i ); MSB means for identifying which of said first or second adjacent pairs of digital sample signals (S i , S i-1 ) is selected by said selection means; and dual clocking means for stepping the input of said decimation means at said transfer rate F s =2F d and for stepping the output of said decimation means at said data rate F d .
Claim 22
Dependent Claim
108 words
The ADTD of claim 12 wherein said time generator means comprises: reciprocal map means for creating a reciprocal digital signal |S i-1 -S i | -1 representing the reciprocal of the absolute value of the difference between said adjacent pair of digital sample signals (S i , S i-1 ); and multiplier means for multiplying said reciprocal digital signal |S i-1 -S i | -1 by the absolute value of said earlier digital sample signal |S i-1 | to obtain said digital signal representing the ratio t/T d =|S i-1 |.|S i-1 -S i | -1 of said threshold transition time t to said interval T d .
Claim 23
Dependent Claim
241 words
In an optical Pulse Width Modulated (PWM) storage device recording channel wherein digital data stored as a series of signal transitions in said optical medium are read by sensing said transitions to create a signal waveform having a data clock rate F d equal to the reciprocal of a data clock interval T d and having transitions through a first threshold, said data being recovered in said channel, an Asynchronous Digital Threshold Detector (ADTD) comprising: input means for accepting a plurality of digital sample signals {S} at a transfer rate F 2 =2F d representing a sequence of instantaneous values of said signal waveform; transition detection means coupled to said input means for assembling an adjacent pair of said digital sample signals (S i , S i-1 ) and creating a detection flag DF i responsive to a sign difference between said adjacent pair of digital sample signals (S i , S i-1 ); decimation means coupled to said transition detection means for reducing said transfer rate F s of said digital sample signals from 2F d to said data clock rate F d ; and time generator means coupled to said decimation means for interpolating said threshold transition time t within an interval T d equal to the reciprocal of said data clock rate F d and for creating a digital signal representative of the ratio t/T d of said threshold transition time t to said interval T d .
Claim 24
Dependent Claim
241 words
In an optical Pulse Width Modulated (PWM) storage device recording channel wherein digital data stored as a series of signal transitions in said optical medium are read by sensing said transitions to create a signal waveform having a data clock rate F d equal to the reciprocal of a data clock interval T d and having transitions through a first threshold, said data being recovered in said channel, an Asynchronous Digital Threshold Detector (ADTD) comprising: input means for accepting a plurality of digital sample signals {S} at a transfer rate F 2 =2F d representing a sequence of instantaneous values of said signal waveform; transition detection means coupled to said input means for assembling an adjacent pair of said digital sample signals (S i , S i-1 ) and creating a detection flag DF i responsive to a sign difference between said adjacent pair of digital sample signals (S i , S i-1 ); decimation means coupled to said transition detection means for reducing said transfer rate F s of said digital sample signals from 2F d to said data clock rate F d ; and time generator means coupled to said decimation means for interpolating said threshold transition time t within an interval T d equal to the reciprocal of said data clock rate F d and for creating a digital signal representative of the ratio t/T d of said threshold transition time t to said interval T d .
Claim 25
Dependent Claim
33 words
The ADTD of claim 20 wherein said input means further comprises: means for accepting a pulse qualification flag representing that said threshold transition results from a signal pulse rather than a noise pulse.
Claim 26
Dependent Claim
129 words
The ADTD of claim 21 wherein said transition detection means comprises: first register means for storing the earlier said digital sample signal S i-1 of said adjacent pair of digital sample signals (S i , S i-1 ); second register means for storing the later said digital sample signal S i of said adjacent pair of digital sample signals (S i , S i-1 ); sign comparator means for creating a signal corresponding to the logical exclusive-or of the signs of said adjacent pair of digital sample signals (S i , S i-1 ); and detection qualification means for enabling the output from said sign comparator means responsive to both said pulse qualification flags corresponding to said adjacent pair of digital sample signals (S i , S i-1 ).
Claim 27
Dependent Claim
134 words
The ADTD of claim 22 wherein said decimation means comprises: third register means for storing said adjacent pair of digital sample signals (S i , S i-1 ); selection means for selecting within one said interval T d either a first said adjacent pair of digital sample signals (S i , S i-1 ) or a second said adjacent pair of digital sample signals (S i+1 , S i ); MSB means for identifying which of said first or second adjacent pairs of digital sample signals (S i , S i-1 ) is selected by said selection means; and dual clocking means for stepping the input of said decimation means at said transfer rate F s =2F d and for stepping the output of said decimation means at said data rate F d .
Claim 28
Dependent Claim
108 words
The ADTD of claim 23 wherein said time generator means comprises: reciprocal map means for creating a reciprocal digital signal |S i-1 -S i | -1 representing the reciprocal of the absolute value of the difference between said adjacent pair of digital sample signals (S i , S i-1 ); and multiplier means for multiplying said reciprocal digital signal |S i-1 -S i | -1 by the absolute value of said earlier digital sample signal |S i-1 | to obtain said digital signal representing the ratio t/T d =|S i-1 |.|S i-1 -S i | -1 of said threshold transition time t to said interval T d .
Claim 29
Dependent Claim
129 words
The ADTD of claim 20 wherein said transition detection means comprises: first register means for storing the earlier said digital sample signal S i-1 of said adjacent pair of digital sample signals (S i , S i-1 ); second register means for storing the later said digital sample signal S i of said adjacent pair of digital sample signals (S i , S i-1 ); sign comparator means for creating a signal corresponding to the logical exclusive-or of the signs of said adjacent pair of digital sample signals (S i , S i-1 ); and detection qualification means for enabling the output from said sign comparator means responsive to both said pulse qualification flags corresponding to said adjacent pair of digital sample signals (S i , S i-1 ).
Claim 30
Dependent Claim
134 words
The ADTD of claim 20 wherein said decimation means comprises: third register means for storing said adjacent pair of digital sample signals (S i , S i-1 ); selection means for selecting within one said interval T d either a first said adjacent pair of digital sample signals (S i , S i-1 ) or a second said adjacent pair of digital sample signals (S i+1 , S i ); MSB means for identifying which of said first or second adjacent pairs of digital sample signals (S i , S i-1 ) is selected by said selection means; and dual clocking means for stepping the input of said decimation means at said transfer rate F s =2F d and for stepping the output of said decimation means at said data rate F d .
Claim 31
Dependent Claim
108 words
The ADTD of claim 20 wherein said time generator means comprises: reciprocal map means for creating a reciprocal digital signal |S i-1 -S i | -1 representing the reciprocal of the absolute value of the difference between said adjacent pair of digital sample signals (S i , S i-1 ); and multiplier means for multiplying said reciprocal digital signal |S i-1 -S i | -1 by the absolute value of said earlier digital sample signal |S i-1 | to obtain said digital signal representing the ratio t/T d =|S i-1 |.|S i-1 -S i | -1 of said threshold transition time t to said interval T d .
Claim 32
Dependent Claim
239 words
In a data storage tape drive magnetic recording channel wherein digital data stored as a series of signal transitions in said magnetic tape are read by sensing said transitions to create a signal waveform having a data clock rate F d equal to the reciprocal of a data clock interval T d and having transitions through a first threshold, said data being recovered in said channel, an Asynchronous Digital Threshold Detector (ADTD) comprising: input means for accepting a plurality of digital sample signals {S} at a transfer rate F s =2F d representing a sequence of instantaneous values of said signal waveform; transition detection means coupled to said input means for assembling an adjacent pair of said digital sample signals (S i , S i-1 ) and creating a detection flag DF i responsive to a sign difference between said adjacent pair of digital sample signals (S i , S i-1 ); decimation means coupled to said transition detection means for reducing said transfer rate F s of said digital sample signals from 2F d to said data clock rate F d ; and time generator means coupled to said decimation means for interpolating said threshold transition time t within an interval T d equal to the reciprocal of said data clock rate F d and for creating a digital signal representative of the ratio t/T d of said threshold transition time t to said interval T d .
Claim 33
Dependent Claim
239 words
In a data storage tape drive magnetic recording channel wherein digital data stored as a series of signal transitions in said magnetic tape are read by sensing said transitions to create a signal waveform having a data clock rate F d equal to the reciprocal of a data clock interval T d and having transitions through a first threshold, said data being recovered in said channel, an Asynchronous Digital Threshold Detector (ADTD) comprising: input means for accepting a plurality of digital sample signals {S} at a transfer rate F s =2F d representing a sequence of instantaneous values of said signal waveform; transition detection means coupled to said input means for assembling an adjacent pair of said digital sample signals (S i , S i-1 ) and creating a detection flag DF i responsive to a sign difference between said adjacent pair of digital sample signals (S i , S i-1 ); decimation means coupled to said transition detection means for reducing said transfer rate F s of said digital sample signals from 2F d to said data clock rate F d ; and time generator means coupled to said decimation means for interpolating said threshold transition time t within an interval T d equal to the reciprocal of said data clock rate F d and for creating a digital signal representative of the ratio t/T d of said threshold transition time t to said interval T d .
Claim 34
Dependent Claim
33 words
The ADTD of claim 28 wherein said input means further comprises: means for accepting a pulse qualification flag representing that said threshold transition results from a signal pulse rather than a noise pulse.
Claim 35
Dependent Claim
129 words
The ADTD of claim 29 wherein said transition detection means comprises: first register means for storing the earlier said digital sample signal S i-1 of said adjacent pair of digital sample signals (S i , S i-1 ); second register means for storing the later said digital sample signal S i of said adjacent pair of digital sample signals (S i , S i-1 ); sign comparator means for creating a signal corresponding to the logical exclusive-or of the signs of said adjacent pair of digital sample signals (S i , S i-1 ); and detection qualification means for enabling the output from said sign comparator means responsive to both said pulse qualification flags corresponding to said adjacent pair of digital sample signals (S i , S i-1 ).
Claim 36
Dependent Claim
134 words
The ADTD of claim 30 wherein said decimation means comprises: third register means for storing said adjacent pair of digital sample signals (S i , S i-1 ); selection means for selecting within one said interval T d either a first said adjacent pair of digital sample signals (S i , S i-1 ) or a second said adjacent pair of digital sample signals (S i+1 , S i ); MSB means for identifying which of said first or second adjacent pairs of digital sample signals (S i , S i-1 ) is selected by said selection means; and dual clocking means for stepping the input of said decimation means at said transfer rate F s =2F d and for stepping the output of said decimation means at said data rate F d .
Claim 37
Dependent Claim
108 words
The ADTD of claim 31 wherein said time generator means comprises: reciprocal map means for creating a reciprocal digital signal |S i-1 -S i | -1 representing the reciprocal of the absolute value of the difference between said adjacent pair of digital sample signals (S i , S i-1 ); and multiplier means for multiplying said reciprocal digital signal |S i-1 -S i | -1 by the absolute value of said earlier digital sample signal |S i-1 | to obtain said digital signal representing the ratio t/T d =|S i-1 |.|S i-1 -S i | -1 of said threshold transition time t to said interval T d .
Claim 38
Dependent Claim
129 words
The ADTD of claim 28 wherein said transition detection means comprises: first register means for storing the earlier said digital sample signal S i-1 of said adjacent pair of digital sample signals (S i , S i-1 ); second register means for storing the later said digital sample signal S i of said adjacent pair of digital sample signals (S i , S i-1 ); sign comparator means for creating a signal corresponding to the logical exclusive-or of the signs of said adjacent pair of digital sample signals (S i , S i-1 ); and detection qualification means for enabling the output from said sign comparator means responsive to both said pulse qualification flags corresponding to said adjacent pair of digital sample signals (S i , S i-1 ).
Claim 39
Dependent Claim
134 words
The ADTD of claim 28 wherein said decimation means comprises: third register means for storing said adjacent pair of digital sample signals (S i , S i-1 ); selection means for selecting within one said interval T d either a first said adjacent pair of digital sample signals (S i , S i-1 ) or a second said adjacent pair of digital sample signals (S i+1 , S i ); MSB means for identifying which of said first or second adjacent pairs of digital sample signals (S i , S i-1 ) is selected by said selection means; and dual clocking means for stepping the input of said decimation means at said transfer rate F s =2F d and for stepping the output of said decimation means at said data rate F d .
Claim 40
Dependent Claim
108 words
The ADTD of claim 28 wherein said time generator means comprises: reciprocal map means for creating a reciprocal digital signal |S i-1 -S i | -1 representing the reciprocal of the absolute value of the difference between said adjacent pair of digital sample signals (S i , S i-1 ); and multiplier means for multiplying said reciprocal digital signal |S i-1 -S i | -1 by the absolute value of said earlier digital sample signal |S i-1 | to obtain said digital signal representing the ratio t/T d =|S i-1 |.|S i-1 -S i | -1 of said threshold transition time t to said interval T d .
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-05-23 | 1997-11-22 | 1998-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-23 | 2001-11-22 | 2002-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-23 | 2005-11-22 | 2006-05-24 | $7700.00 | Window Closed / Lapsed |