US5313648A
Expired / Lapsed
US
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Signal processing apparatus having first and second registers enabling both to concurrently receive identical information in one context and disabling one to retain the information in a next context
Assignee: Texas Instruments Inc
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Filing: 1992-10-09
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Granted: 1994-05-17
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Expires: 2012-10-09
Abstract
Abstract A signal processing apparatus includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.
Inventors
- 👤 Peter N. Ehlig
- 👤 Fredric Boutaud
- 👤 James F. Hollander
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 06:19
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F11/3652; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318536; G06F11/22; G06F11/2205; G06F11/2236; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/30014; G06F9/30021; G06F9/30098; G06F9/30101; G06F9/46; G06F9/461; G06F9/462; G01R31/318505; G06F11/26; G06F11/273; G06F11/2733
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
201 words
A signal processing apparatus comprising: an analog-to-digital converter for producing a digital signal corresponding to an analog input by a conversion process and for producing an interrupt signal when a conversion is complete; a digital processing device having a memory; and a processor connecting to said analog-to-digital converter and responsive to said interrupt signal for entering the digital signal into the memory in alternative processing contexts identified by a state of said interrupt signal; and said processor including: a multiplier; an arithmetic logic unit; a plurality of register sets, each of said register sets having a first and second register, said first and second registers connected to concurrently store identical information during one of the processing contexts, said first register connected to individually participate and be continuously available in a next of the processing contexts when said first register is selected thereby enabling the second register to retain said information from said one processing context; and a context switching circuit responsive to the state of said interrupt signal and connected to said first and second registers to alternatively control input and output operations of said register set to and from said multiplier and arithmetic logic unit depending on the processing context.
Claim 2
Dependent Claim
201 words
A signal processing apparatus comprising: an analog-to-digital converter for producing a digital signal corresponding to an analog input by a conversion process and for producing an interrupt signal when a conversion is complete; a digital processing device having a memory; and a processor connecting to said analog-to-digital converter and responsive to said interrupt signal for entering the digital signal into the memory in alternative processing contexts identified by a state of said interrupt signal; and said processor including: a multiplier; an arithmetic logic unit; a plurality of register sets, each of said register sets having a first and second register, said first and second registers connected to concurrently store identical information during one of the processing contexts, said first register connected to individually participate and be continuously available in a next of the processing contexts when said first register is selected thereby enabling the second register to retain said information from said one processing context; and a context switching circuit responsive to the state of said interrupt signal and connected to said first and second registers to alternatively control input and output operations of said register set to and from said multiplier and arithmetic logic unit depending on the processing context.
Claim 3
Dependent Claim
40 words
The apparatus of claim 1 wherein said context switching circuit includes a multiplexer and a control circuit for operating said multiplexer, the processor and one of the registers respectively supplying information for selection by said multiplexer for the other register.
Claim 4
Dependent Claim
22 words
The apparatus of claim 1 wherein the first and second registers both have inputs connected to receive information simultaneously from said processor.
Claim 5
Dependent Claim
41 words
The apparatus of claim 1, said context switching circuit including an electronic switch; and, a control circuit; said electronic switch selectively connecting said processor to the first or second register alternatively, depending on the context of operation and said control circuit.
Claim 6
Dependent Claim
17 words
The apparatus of claim 1, said context switching circuit for selectively clocking said first and second registers.
Claim 7
Dependent Claim
41 words
The apparatus of claim 5, said first and second registers having outputs connected together and to said processor, and said context switching circuit for selectively enabling an output operation from said first or second register, depending on the context of operation.
Claim 8
Dependent Claim
37 words
The apparatus of claim 1 further comprising a multiplexor, said first and second registers having respective outputs connected to said multiplexor, said multiplexor for selectively connecting said outputs to said processor responsive to said context switching circuit.
Claim 9
Dependent Claim
25 words
The apparatus of claim 1 wherein said first register is operated as a main register and said second register is operated as a counterpart register.
Claim 10
Dependent Claim
55 words
The apparatus of claim 1 wherein said first register alternately acts as a main register and then a counterpart register while said second register correspondingly acts as a counterpart register when said first register acts as a main register and then acts as a main register when said first register acts as a counterpart register.
Claim 11
Dependent Claim
176 words
A signal processing apparatus with context switching including: an analog-to-digital converter for producing a digital signal responsive to an input analog signal and an interrupt signal indicating that the digital signal is available for processing; and a digital processing device having a processor for processing said digital signal in alternative processing contexts identified by a state of said interrupt signal; said processor including: a plurality of register sets, each of said register sets having a first and second register, said first and second registers connected to concurrently store identical information during one of the processing contexts, said first register connected to individually participate and be continuously available in a next of the processing contexts when said first register is selected thereby enabling the second register to retain said information from said one processing context; and a context switching circuit responsive to the state of said interrupt signal and connected to said first and second registers to alternatively control input and output operations of said register set to and from said processor depending on the processing context.
Claim 12
Dependent Claim
176 words
A signal processing apparatus with context switching including: an analog-to-digital converter for producing a digital signal responsive to an input analog signal and an interrupt signal indicating that the digital signal is available for processing; and a digital processing device having a processor for processing said digital signal in alternative processing contexts identified by a state of said interrupt signal; said processor including: a plurality of register sets, each of said register sets having a first and second register, said first and second registers connected to concurrently store identical information during one of the processing contexts, said first register connected to individually participate and be continuously available in a next of the processing contexts when said first register is selected thereby enabling the second register to retain said information from said one processing context; and a context switching circuit responsive to the state of said interrupt signal and connected to said first and second registers to alternatively control input and output operations of said register set to and from said processor depending on the processing context.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-16 | 1997-11-15 | 1998-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-16 | 2001-11-15 | 2002-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-16 | 2005-11-15 | 2006-05-17 | $7700.00 | Window Closed / Lapsed |