Multiplexer

Claim 1

Multiplexer for selecting m contiguous information units stored in m adjacent subsections of a first register containing n subsections and transferring said m information units to a second register containing m subsections, where m is less than n and n is greater than one, said multiplexer comprising: k logic stages which each contain z(x) submultiplexers compressing in the ratio q(x):1; wherein x is a variable from 1 to k; the first logic stage contains between n and m+(q(k)*q(k-1)* . . . *q(3)*q(2))-1 submultiplexers; the kth logic stage contains m submultiplexers; the xth logic stage contains between n and m+(q(k)*q(k-1)* . . . *q([k-]x+1))-1 submultiplexers for k>x>1; the outputs of the kth logic stage submultiplexers are connected to the inputs of the second register; the hth input to the ith submultiplexer in the xth logic stage is connected to the output of the i+(h-1)*(q(x+1)*q(x+2)* . . . *q(k))[-1] submultiplexer in the previous, (x-1)th, logic stage; and n is less than or equal to the product q(1)*q(2)* . . . *q(k-1)*q(k).