Abstract A method of forming a closely spaced self-aligned polysilicon pattern of conductive lines is achieved. The method involves forming semiconductor device structures in and on a semiconductor substrate. An insulating layer is formed over the device structures. An insulating layer structure is formed over the semiconductor device structures. A conductive polysilicon layer is formed over the insulating layer. A silicon oxide layer is formed over the polysilicon layer. The oxide layer is now patterned by lithography and etching. The patterning of the oxide layer leaves a first pattern of the oxide over a first designated plurality of polysilicon conductor lines and a second pattern between the oxide which exposes the polysilicon layer over a second designated plurality of polysilicon conductor lines plus the planned spacing between the first and second plurality of polysilicon conductor lines. A uniform thickness silicon nitride layer is deposited over the oxide layer and the exposed polysilicon layer wherein the thickness is the width of the planned spacing. The nitride layer is anisotropically etched to produce sidewall structures having the width of the planned spacing. The exposed polysilicon layer is oxidized to form a silicon oxide layer thereon. The sidewall structures are removed by etching. The exposed polysilicon layer is anisotropically etched to form the closely spaced polysilicon conductor lines. The oxide layers over the polysilicon conductor lines are removed as by etching.
The method of manufacturing single level polysilicon conductor lines in a EPROM integrated circuit comprising: forming buried regions of a conductivity type in an opposite conductivity type semiconductor substrate; forming an insulating layer structure over said semiconductor substrate; forming floating gate and gate dielectric layer structures on the surface of said semiconductor substrate; forming a conductive polysilicon layer over said gate dielectric layer which comprises a first and a second designated plurality of polysilicon conductive lines; forming a silicon oxide layer over said polysilicon layer and patterning said oxide layer; said oxide layer is patterned such that it covers the first designated plurality of polysilicon conductive lines and exposes the second designated plurality of polysilicon conductive lines and the portion of the polysilicon conductive layer which will be removed to provide planned spacing between the first and second designated pluralities of polysilicon conductive lines; depositing a uniform thickness silicon nitride layer over said oxide layer and said exposed polysilicon layer wherein said thickness is the width of said planned spacing; anisotropically etching said nitride layer to produce sidewall structures having the width of said planned spacing; oxidizing the exposed portion of said polysilicon layer; removing said sidewall structures by etching; anisotropically etching the resulting exposed said polysilicon layer to form said single level polysilicon conductor lines; removing the remaining portions of said oxide layer; and electrically connecting said polysilicon lines to form word lines and said floating gate structures and said buried regions as bit lines to form said EPROM integrated circuit.
Claim 2
Independent Claim
252 words
The method of manufacturing single level polysilicon conductor lines in a EPROM integrated circuit comprising: forming buried regions of a conductivity type in an opposite conductivity type semiconductor substrate; forming an insulating layer structure over said semiconductor substrate; forming floating gate and gate dielectric layer structures on the surface of said semiconductor substrate; forming a conductive polysilicon layer over said gate dielectric layer which comprises a first and a second designated plurality of polysilicon conductive lines; forming a silicon oxide layer over said polysilicon layer and patterning said oxide layer; said oxide layer is patterned such that it covers the first designated plurality of polysilicon conductive lines and exposes the second designated plurality of polysilicon conductive lines and the portion of the polysilicon conductive layer which will be removed to provide planned spacing between the first and second designated pluralities of polysilicon conductive lines; depositing a uniform thickness silicon nitride layer over said oxide layer and said exposed polysilicon layer wherein said thickness is the width of said planned spacing; anisotropically etching said nitride layer to produce sidewall structures having the width of said planned spacing; oxidizing the exposed portion of said polysilicon layer; removing said sidewall structures by etching; anisotropically etching the resulting exposed said polysilicon layer to form said single level polysilicon conductor lines; removing the remaining portions of said oxide layer; and electrically connecting said polysilicon lines to form word lines and said floating gate structures and said buried regions as bit lines to form said EPROM integrated circuit.
Claim 3
Dependent Claim
29 words
The method of claim 1 wherein said polysilicon layer has a thickness of between about 2000 to 4000 Angstroms and is doped with phosphorus after deposition using phosphorus oxychloride.
Claim 4
Dependent Claim
22 words
The method of claim 1 wherein said silicon oxide layer is formed to a thickness of between about 2000 to 4000 Angstroms.
Claim 5
Dependent Claim
20 words
The method of claim 1 wherein said silicon nitride layer has a thickness of between about 1000 to 3000 Angstroms.
Claim 6
Dependent Claim
19 words
The method of claim 1 wherein said anisotropic etching ambient for etching said polysilicon layer is composed of chlorine/helium.
Claim 7
Dependent Claim
22 words
The method of claim 1 wherein said etching of said silicon nitride to form said sidewall layer is done using phosphoric acid.