US5309387A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Tamper resistant module with logical elements arranged on a substrate to protect information stored in the same module
Assignee: Individual
•
Filing: 1992-11-06
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Granted: 1994-05-03
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Expires: 2012-11-06
Abstract
Abstract The reliability of a tamper resistant module for safeguarding stored information, e.g. in an electronic computer system, is improved to deny access to the system by an unauthorized person or at least to a specific portion of the system. For this purpose, the module has for example a pair of substrates which are bonded together to confine confidential data inside the module. On the outer surfaces of the substrates, a plurality of logical elements, such as transistors, form detecting memory devices. The plurality of these detecting memory devices are operative under a normal condition, but at least one of these detecting memory devices is rendered inoperative when a tampering is applied to the outer surface of the substrate. In a tamper free normal situation all memory devices work properly. The inoperability of any of the detecting memory devices is detected when tampering occurs. When the tamper is detected, the confidential data confined within the module are erased.
Inventors
- 👤 Ryoichi Mori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:09
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/24; G06; G06F; G06F21/00; G06F21/70; G06F21/86; G06F21/87; G06F2221/00; G06F2221/21; G06F2221/2143
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
182 words
A tamper resistant module for safeguarding stored confidential information, comprising substrate means having an inner surface and an outer surface, memory means supported on said inner surface of said substrate means for storing said confidential information in said memory means means supported on said outer surface of said substrate means for providing a testing value, tamper detection circuit means on said inner surface connected to said testing value providing means and to said memory means for erasing said confidential information from said memory means when a tamper is detected in response to said testing value, said tamper detection circuit means comprising address generating circuit means connected to said testing value providing means for supplying address signals to said testing value providing means, a reading circuit connected to said testing value providing means for reading said testing value from said testing value providing means, and testing value comparing circuit means connected to said reading circuit for comparing values from said reading to provide a tamper detection signal if there is any difference between values from said testing value and from said reading circuit.
Claim 2
Dependent Claim
182 words
A tamper resistant module for safeguarding stored confidential information, comprising substrate means having an inner surface and an outer surface, memory means supported on said inner surface of said substrate means for storing said confidential information in said memory means means supported on said outer surface of said substrate means for providing a testing value, tamper detection circuit means on said inner surface connected to said testing value providing means and to said memory means for erasing said confidential information from said memory means when a tamper is detected in response to said testing value, said tamper detection circuit means comprising address generating circuit means connected to said testing value providing means for supplying address signals to said testing value providing means, a reading circuit connected to said testing value providing means for reading said testing value from said testing value providing means, and testing value comparing circuit means connected to said reading circuit for comparing values from said reading to provide a tamper detection signal if there is any difference between values from said testing value and from said reading circuit.
Claim 3
Dependent Claim
81 words
The tamper resistant module of claim 1, further comprising a writing circuit connected to said testing value providing means for writing said testing value into an address of said testing value providing means, said testing value comparing circuit means being connected to said writing circuit and to said reading circuit for comparing values from said reading and writing circuits to provide a tamper detection signal if there is no coincidence between values from said writing circuit and from said reading circuit.
Claim 4
Dependent Claim
34 words
The tamper resistant module of claim 1, further comprising erasing circuit means connected to said comparing circuit and to said memory means for erasing said confidential information in response to said tamper detection signal.
Claim 5
Dependent Claim
30 words
The tamper resistant module of claim 1, wherein said testing value providing means comprise of a plurality of logical elements arranged in at least two layers on said substrate means.
Claim 6
Dependent Claim
16 words
The tamper resistant module of claim 1, wherein said testing value providing means comprise a ROM.
Claim 7
Dependent Claim
20 words
The tamper resistant module of claim 1, wherein said testing value providing means comprise an erasable, programmable read-only memory (EPROM).
Claim 8
Dependent Claim
17 words
The tamper resistant module of claim 2, wherein said testing value providing means comprise a dynamic RAM.
Claim 9
Dependent Claim
17 words
The tamper resistant module of claim 2, wherein said testing value providing means comprise a static RAM.
References Cited (Backward Citations)
US5245582A
Cited
US5185717A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-02 | 1997-11-01 | 1998-05-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-02 | 2001-11-01 | 2002-05-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-02 | 2005-11-01 | 2006-05-03 | $7700.00 | Window Closed / Lapsed |