US5309258A
Expired / Lapsed
US
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Pattern image generation device for image processing system
Assignee: Fujifilm Business Innovation Corp
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Filing: 1992-09-11
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Granted: 1994-05-03
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Expires: 2012-09-11
Abstract
Abstract A pattern image generation device which is able to generate various patterns by use of a RAM for processing ordinary image data and also is able to generate the patterns in a simple structure. The pattern image generation device includes an image conversion processor for converting an input image data signal to output a converted image data, the image conversion processor including rewritable memory and address controller for controlling a memory address of said memory, and an operation processor for controlling the operation of the image conversion processor.
Inventors
- 👤 Katsuyuki Kouno
- 👤 Kazuhisa Sato
- 👤 Masayasu Kurosawa
- 👤 Isao Kuwahara
- 👤 Mitsuo Fukitomi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:37
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/40; H04N1/405; H04N1/4055; H04N1/46; H04N1/56; H04N1/60; H04N1/6016; H04N1/6022; H04N1/6025
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
206 words
A pattern image generation device for a color image processing system comprising: an image conversion processing means for converting an input image data signal to output a converted image data, said image conversion processing means including rewritable memory means and address control means for controlling a memory address of said memory means; and an operation processing means for controlling the operation of said image conversion processing means; said address control means including a variable address generation means for generating a variable address signal in accordance with a synchronizing signal output from said operation processing means, and a signal select means for selecting one of said input image data signal, an address signal output from said operation processing means and said variable address signal in accordance with a control signal from said operation processing means, and wherein said operation processing means outputs to said memory means one of conversion data used to convert said input image data signal to be set in said memory means and predetermined pattern generation data to be set in said memory means in synchronization with said control signal, and said operation processing means controls said signal select means to select one of said input image data signal and said variable address signal.
Claim 2
Dependent Claim
206 words
A pattern image generation device for a color image processing system comprising: an image conversion processing means for converting an input image data signal to output a converted image data, said image conversion processing means including rewritable memory means and address control means for controlling a memory address of said memory means; and an operation processing means for controlling the operation of said image conversion processing means; said address control means including a variable address generation means for generating a variable address signal in accordance with a synchronizing signal output from said operation processing means, and a signal select means for selecting one of said input image data signal, an address signal output from said operation processing means and said variable address signal in accordance with a control signal from said operation processing means, and wherein said operation processing means outputs to said memory means one of conversion data used to convert said input image data signal to be set in said memory means and predetermined pattern generation data to be set in said memory means in synchronization with said control signal, and said operation processing means controls said signal select means to select one of said input image data signal and said variable address signal.
Claim 3
Dependent Claim
39 words
A pattern image generation device for an image processing system as defined in claim 1 wherein said variable address generation means comprises a plurality of count modes to select a pattern to be generated by switching the count modes.
Claim 4
Dependent Claim
32 words
A pattern image generation device for an image processing system as defined in claim 2 wherein said variable address generation means comprises a mode to update an address every given block size.
Claim 5
Dependent Claim
37 words
A pattern image generation device for an image processing system as defined in claim 2 wherein said variable address generation means comprises a mode to inert a line by means of different repeat addresses every given line.
Claim 6
Dependent Claim
38 words
A pattern image generation device for an image processing system as defined in claim 2 wherein said variable address generation means comprises a mode to generate the leading addresses of the respective lines in a sequentially staggering manner.
Claim 7
Dependent Claim
68 words
A pattern image generation device for an image processing system as defined in claim 1 wherein said image conversion processing part comprises a conversion table used to convert input image data, said conversion table including a circuit used to write the input image data, and said address control means controlling a write address to write the input image data into said conversion table and to read data therefrom.
Claim 8
Dependent Claim
52 words
A pattern image generation device for an image processing systems as defined in claim 1 wherein said address control means comprises a plurality of pattern generating data for every given address width, said address control means writing said plurality of data and fixed data into said conversion table in a given sequence.
Claim 9
Dependent Claim
49 words
A pattern image generation device for an image processing system as defined in claim 1 wherein said conversion processing means comprises a matrix conversion circuit for conversion of the coordinates of the image data to generate patterns by setting matrix coefficients and constants by means of pattern generating data.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-02 | 1997-11-01 | 1998-05-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-02 | 2001-11-01 | 2002-05-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-02 | 2005-11-01 | 2006-05-03 | $7700.00 | Window Closed / Lapsed |