Variable-length code decoding device

Claim 1

A variable-length code decoding device comprising: converter means for converting serial data into parallel data for every N bits where N is an integer, said serial data including consecutive data pieces having variable data lengths; buffer memory means, coupled to said converter means, for storing the parallel data which is sequentially read out therefrom for every N bits and which is shifted by N bits in a high-order-bit direction in response to a carry signal; register means for storing a shifted number "j" which is read out therefrom in response to a clock signal, said shifted number "j" indicating the number of bits to be shifted; barrel shifter means, coupled to said buffer memory means, for receiving the parallel data from the buffer memory means and for shifting, by the shifted number "j", the parallel data in the high-order-bit direction so that N-bit parallel data having a starting bit which corresponds to an (j+1)th bit of the parallel data from a most significant bit thereof is output from said barrel shifter means; and shifted number/carry signal generator means, coupled to said barrel shifter means and said register means, for generating, on the basis of a code length of effective data contained in said N-bit parallel data and the shifted number stored in the register means, an updated shifted number and said carry signal, said shifted number stored in the register means being updated by said updated shifted number, said shifted number/carry signal generator including memory means for storing combinations of the updated shifted number and the carry signal corresponding to all combinations of data lengths of possible effective data and the shifted number and wherein the code length of the effective data contained in said N-bit parallel data and the shifted number stored in the register means are input, as an address signal, to said memory means.