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US5307407A Expired / Lapsed US ⏱️ 0.0 years remaining

20 Hz ring generator using high frequency PWM control

Assignee: NEC Corp of America
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Filing: 1991-12-19
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Granted: 1994-04-26
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Expires: 2011-12-19
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Abstract

Abstract A low frequency high voltage AC power for a telephone system is provided by a ring signal generator, which produces a ring signal from a DC power supply using a pair of switches controlled by pulse width modulation (PWM) circuit. The ring signal generator includes a PWM circuit driving a pair of MOSFET transistors via a respective pair of opto-isolators. The output of the MOSFET transistor switches is commonly connected to a low pass filter network. The ring signal generator of the present invention advantageously produces a 65 VRMS ring signal at very high efficiency.

Inventors

  • 👤 Rolf H. G. Wendt
  • 👤 Steven E. Hossner

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 12:20
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/53; H02M7/537; H02M7/538; H04; H04M; H04M19/00; H04M19/02

Claims Analysis

Total Claims: 23
Claim 1
Independent Claim 180 words
A ring signal generator producing a high voltage sinusoidal waveform at a predetermined frequency from first and second rails providing high DC voltages of opposite polarity, said ring signal generator comprising: first and second switch elements commonly connected to a low pass filter and connected to the first and second rails, respectively; first and second opto-isolators coupled to said first and second switch elements, respectively, for allowing operation of said first and second switch elements responsive to first and second pulse modulated signals transmitted by said first and second opto-isolators, respectively; first and second comparators respectively coupled to said first and second opto-isolators for generating said first and second pulse modulated signals, respectively, based on an error signal and a second signal, wherein the operating frequency of said second signal is significantly higher than the frequency of said error signal and wherein said error signal is based on a difference between a reference signal having a frequency substantially equal to said frequency of said error signal and a feedback signal corresponding to an output signal of said low pass filter.
Claim 2
Dependent Claim 180 words
A ring signal generator producing a high voltage sinusoidal waveform at a predetermined frequency from first and second rails providing high DC voltages of opposite polarity, said ring signal generator comprising: first and second switch elements commonly connected to a low pass filter and connected to the first and second rails, respectively; first and second opto-isolators coupled to said first and second switch elements, respectively, for allowing operation of said first and second switch elements responsive to first and second pulse modulated signals transmitted by said first and second opto-isolators, respectively; first and second comparators respectively coupled to said first and second opto-isolators for generating said first and second pulse modulated signals, respectively, based on an error signal and a second signal, wherein the operating frequency of said second signal is significantly higher than the frequency of said error signal and wherein said error signal is based on a difference between a reference signal having a frequency substantially equal to said frequency of said error signal and a feedback signal corresponding to an output signal of said low pass filter.
Claim 3
Dependent Claim 33 words
The ring signal generator of claim 1, further comprising a first differential amplifier connected so as to receive said reference signal and said feedback signal and so as to output said error signal.
Claim 4
Dependent Claim 33 words
The ring signal generator of claim 2, further comprising a second differential amplifier connected so as to receive said output signal and a DC signal and so as to output said feedback signal.
Claim 5
Dependent Claim 26 words
The ring signal generator of claim 1, further comprising: a first generator for generating said reference signal; and a second generator for generating said second signal.
Claim 6
Dependent Claim 55 words
The ring signal generator of claim 1, wherein said error signal comprises first and second error signals and wherein said ring signal generator further comprises a voltage divider network connected so as to receive said error signal and so as to output said first and second error signals to said first and second comparators, respectively.
Claim 7
Dependent Claim 16 words
The ring signal generator of claim 1, wherein said low pass filter comprises an inductance-capacitance network.
Claim 8
Dependent Claim 79 words
The ring signal generator of claim 1, further comprising: first and second logical elements serially connected between respective ones of said first and second comparators and said first and second opto-isolators; and a control circuit operatively coupled to said first and second logical elements so as to permit at least one control signal produced by said control circuit to prevent application of at least one of said first and second pulse modulated signals to said first and second opto-isolators.
Claim 9
Dependent Claim 17 words
The ring signal generator of claim 7, wherein said first and second logical elements are NAND gates.
Claim 10
Dependent Claim 19 words
The ring signal generator of claim 1, wherein said first and second switch elements are high voltage MOSFET transistors.
Claim 11
Dependent Claim 270 words
A ring signal generator producing a high voltage sinusoidal waveform at a first predetermined frequency from first and second rails providing high DC voltages of opposite polarity, said ring signal generator comprising: a pulse width modulation circuit connected to receive an error corrected reference signal, which is based on a reference signal and an output signal, and a second signal having a frequency significantly higher than a frequency of said error corrected reference signal for generating first and second pulse modulated signals, said first pulse modulated signal being generated when the amplitude of said error corrected reference signal is greater than said second signal and said second pulse modulated signal being generated when said the amplitude of said second signal is greater than the amplitude of said error corrected reference signal; first and second transistors; first and second opto-isolators serially coupled to said pulse width modulation circuit and respective gates of said first and second transistors so as to permit said first and second pulse modulated signals to be applied to said first and second transistors, respectively; and a filter; wherein source terminals of said first and second transistors are connected to respective ones of the first and second rails and drain terminals of said first and second transistors are connected to an input terminal of said filter network; wherein said first and second transistors generate an unfiltered output signal at a second predetermined frequency responsive to application of said first and second pulse modulated signals to respective gates of said first and second transistors; and wherein said filter network generates said output signal responsive to said unfiltered output signal.
Claim 12
Dependent Claim 270 words
A ring signal generator producing a high voltage sinusoidal waveform at a first predetermined frequency from first and second rails providing high DC voltages of opposite polarity, said ring signal generator comprising: a pulse width modulation circuit connected to receive an error corrected reference signal, which is based on a reference signal and an output signal, and a second signal having a frequency significantly higher than a frequency of said error corrected reference signal for generating first and second pulse modulated signals, said first pulse modulated signal being generated when the amplitude of said error corrected reference signal is greater than said second signal and said second pulse modulated signal being generated when said the amplitude of said second signal is greater than the amplitude of said error corrected reference signal; first and second transistors; first and second opto-isolators serially coupled to said pulse width modulation circuit and respective gates of said first and second transistors so as to permit said first and second pulse modulated signals to be applied to said first and second transistors, respectively; and a filter; wherein source terminals of said first and second transistors are connected to respective ones of the first and second rails and drain terminals of said first and second transistors are connected to an input terminal of said filter network; wherein said first and second transistors generate an unfiltered output signal at a second predetermined frequency responsive to application of said first and second pulse modulated signals to respective gates of said first and second transistors; and wherein said filter network generates said output signal responsive to said unfiltered output signal.
Claim 13
Dependent Claim 59 words
The ring signal generator of claim 10, further comprising: a first differential amplifier connected so as to receive said output signal and a DC signal corresponding to a DC voltage for generating a feedback signal; and a second differential amplifier connected so as to receive said feedback signal and said reference signal for generating said error corrected reference signal.
Claim 14
Dependent Claim 26 words
The ring signal generator of claim 10, further comprising: a first generator for generating said reference signal; and a second generator for generating said second signal.
Claim 15
Dependent Claim 18 words
The ring signal generator of claim 10, wherein said pulse width modulation circuit comprises first and second comparators.
Claim 16
Dependent Claim 63 words
The ring signal generator of claim 13, wherein said error corrected reference signal comprises first and second error corrected reference signals and wherein said ring signal generator further comprises a voltage divider network connected so as to receive said error corrected reference signal and so as to output said first and second error corrected reference signals to said first and second comparators, respectively.
Claim 17
Dependent Claim 105 words
The ring signal generator of claim 10, wherein said pulse width modulation circuit comprises: a voltage divider network having an input terminal connected to receive said error corrected reference signal and generating first and second error corrected reference signals at respective first and second output terminals; and first and second comparators having respective first and second input terminals; wherein said first and second input terminals of said first comparator respectively receive said first error corrected reference signal and said second signal; and wherein said first and second input terminals of said second comparator respectively receive said second signal and said second error corrected reference signal.
Claim 18
Dependent Claim 79 words
The ring signal generator of claim 15, further comprising: first and second logical elements serially connected between respective ones of said first and second comparators and said first and second opto-isolators; and a control circuit operatively coupled to said first and second logical elements so as to permit at least one control signal generated by said control circuit to prevent application of at least one of said first and second pulse modulated signals to said first and second opto-isolators.
Claim 19
Dependent Claim 17 words
The ring signal generator of claim 16, wherein said first and second logical elements are NAND gates.
Claim 20
Dependent Claim 18 words
The ring signal generator of claim 10, wherein said first and second transistors are high voltage MOSFET transistors.
Claim 21
Dependent Claim 440 words
A ring signal generator producing a high voltage sinusoidal waveform at a first predetermined frequency from first and second rails providing high DC voltages of opposite polarity, said ring signal generator comprising: a pulse width modulation circuit connected to receive an error corrected reference signal, which is based on a reference signal and an output signal, and a second signal having a frequency significantly higher than a frequency of said error corrected reference signal and to generate first and second pulse modulated signals, said first pulse modulated signal being generated when the amplitude of said error corrected reference signal is greater than said second signal and said second pulse modulated signal being generated when said the amplitude of said second signal is greater than the amplitude of said error corrected reference signal, said pulse width modulation circuit comprising: a voltage divider having an input terminal connected to receive said error corrected reference signal for generating first and second error corrected reference signals at respective first and second output terminals; first and second comparators having respective first and second input terminals and an output terminal; first and second transistors; first and second opto-isolators serially coupled to respective output terminals of said first and second comparators and respective gates of said first and second transistors so as to permit said first and second pulse modulated signals to be applied to said first and second transistors, respectively; and first and second logical elements serially connected between an output terminal of said first and second comparators and said first and second opto-isolators, respectively; a control circuit operatively coupled to said first and second logical elements for permitting at least one control signal generated by said control circuit to prevent application of said at least one of first and second pulse modulated signals to said first and second opto-isolators; a filter; wherein said first and second input terminals of said first comparator respectively receives said first error corrected reference signal and said second signal and said first and second input terminals of said second comparator respectively receive said second signal and said second error corrected reference signal; wherein source terminals of said first and second transistors are connected to respective ones of the first and second rails and drain terminals of said first and second transistors are connected to an input terminal of said filter; wherein said first and second transistors generate an unfiltered output signal at a second predetermined frequency responsive to application of said first and second pulse modulated signals to respective gates of said first and second transistors; and wherein said filter generates said output signal responsive to said unfiltered output signal.
Claim 22
Dependent Claim 440 words
A ring signal generator producing a high voltage sinusoidal waveform at a first predetermined frequency from first and second rails providing high DC voltages of opposite polarity, said ring signal generator comprising: a pulse width modulation circuit connected to receive an error corrected reference signal, which is based on a reference signal and an output signal, and a second signal having a frequency significantly higher than a frequency of said error corrected reference signal and to generate first and second pulse modulated signals, said first pulse modulated signal being generated when the amplitude of said error corrected reference signal is greater than said second signal and said second pulse modulated signal being generated when said the amplitude of said second signal is greater than the amplitude of said error corrected reference signal, said pulse width modulation circuit comprising: a voltage divider having an input terminal connected to receive said error corrected reference signal for generating first and second error corrected reference signals at respective first and second output terminals; first and second comparators having respective first and second input terminals and an output terminal; first and second transistors; first and second opto-isolators serially coupled to respective output terminals of said first and second comparators and respective gates of said first and second transistors so as to permit said first and second pulse modulated signals to be applied to said first and second transistors, respectively; and first and second logical elements serially connected between an output terminal of said first and second comparators and said first and second opto-isolators, respectively; a control circuit operatively coupled to said first and second logical elements for permitting at least one control signal generated by said control circuit to prevent application of said at least one of first and second pulse modulated signals to said first and second opto-isolators; a filter; wherein said first and second input terminals of said first comparator respectively receives said first error corrected reference signal and said second signal and said first and second input terminals of said second comparator respectively receive said second signal and said second error corrected reference signal; wherein source terminals of said first and second transistors are connected to respective ones of the first and second rails and drain terminals of said first and second transistors are connected to an input terminal of said filter; wherein said first and second transistors generate an unfiltered output signal at a second predetermined frequency responsive to application of said first and second pulse modulated signals to respective gates of said first and second transistors; and wherein said filter generates said output signal responsive to said unfiltered output signal.
Claim 23
Dependent Claim 18 words
The ring signal generator of claim 19, wherein said first and second transistors are high voltage MOSFET transistors.

References Cited (Backward Citations)

US4015091A Cited
US4250455A Cited
US4220826A Cited
US4239935A Cited
US4349703A Cited
US4340785A Cited
US4500844A Cited
US4631361A Cited
US4734936A Cited
US4656659A Cited
US4964158A Cited
US4866587A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-04-25 1997-10-25 1998-04-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-04-25 2001-10-25 2002-04-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-04-25 2005-10-25 2006-04-26 $7700.00 Window Closed / Lapsed

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