Lock apparatus for dual phase locked loop

Claim 2

A lock apparatus for a dual phase locked loop (PLL) comprising: decoding means being operated by an external enable signal to decode channel select data inputted externally thereto, synchronously with a clock pulse; means for generating, transmitting and receiving channel data in accordance with transmitting and receiving frequency select data from said decoding means; transmitting and receiving frequency counting means for determining count values respectively according to the transmitting and receiving channel data from said channel data generating, transmitting and receiving means and for counting, transmitting and receiving frequencies inputted through respective input terminals, respectively, based on the determined count values; transmitting and receiving phase difference detecting means for comparing the counted transmitting and receiving frequencies from said transmitting and receiving frequency counting means with a reference frequency from a reference frequency counter, respectively, to detect phase differences therebetween and for outputting phase data and locked state signals, respectively, based on the detected phase differences; and transmit and receive lock detecting means for detecting phase locked states of the transmitting and receiving frequencies, respectively, in response to the locked state signals from said transmitting and receiving phase difference detecting means and for outputting lock data externally, respectively, in accordance with the detected phase locked states, wherein said receive lock detecting means comprises reset signal generating means for generating a reset signal in response to the receive locked state signal from said receiving phase difference detecting means, frequency-dividing means for dividing a first predetermined frequency from said reference frequency counter by a given ratio in response to the reset signal from said reset signal generating means, and a receive lock data output means for outputting the receive lock data in response to an output signal from said frequency-dividing means.

Claim 3

The lock apparatus for a dual PLL as set forth in claim 1, wherein said reset signal generating means includes: a first inverter gate for invert-buffering the receive locked state signal from said receiving phase difference detecting means; and a first flip-flop for receiving an output signal from said first inverter gate at its data input terminal, an external reset signal at its reset terminal and a second predetermined frequency signal from said reference frequency counter at its clock terminal and outputting the reset signal in response to the output signal from said first inverter gate and synchronously with the second predetermined frequency signal.

Claim 4

The lock apparatus for a dual PLL as set forth in claim 1, wherein said frequency-dividing means includes: a second inverter gate for inverting the first predetermined frequency signal from said reference frequency counter; second and third flip-flops in a master-slave interconnection for receiving the reset signal from said reset signal generating means at their reset terminals and a first output signal from said second inverter gate at their clock terminals, said second and third flip-flops, upon release of reset state, frequency-dividing the output signal from said second inverter gate by two to generate a first frequency-divided signal, delaying the first frequency divided signal by one clock cycle and outputting a first pulse signal delayed by one clock cycle; fourth and fifth flip-flops in a master-slave interconnection for receiving the reset signal from said reset signal generating means at their reset terminals and the first pulse signal delayed by one clock cycle from an inverting output terminal of said third flip-flop at their clock terminals, said fourth and fifth flip-flops, upon release of reset state, frequency-dividing the first pulse signal from said third flip-flop by two to generate a second frequency-divided signal, delaying the second frequency-divided signal by one clock cycle and outputting a second pulse signal delayed by one clock cycle as the output signal; a third inverter gate for inverting the first pulse signal from said inverting output terminal of said third flip-flop to output a second output signal; a fourth inverter gate for inverting the second pulse signal from an inverting output terminal of said fifth flip-flop to output a third output signal; a fifth inverter gate for inverting the third output signal from said fourth inverter gate and feeding back the inverted signal to a data input terminal of said fourth flip-flop; and a NOR gate for NORing the second and third output signals from said third and fourth inverter gates and feeding back the NORed signal to a data input terminal of said second flip-flop.

Claim 5

The lock apparatus for a dual PLL as set forth in claim 1, wherein said receive lock data output means outputs the receive lock data of high impedance in response to the output signal from said frequency-dividing means when the locked state of the receiving frequency is detected.

Claim 6

The lock apparatus for a dual PLL as set forth in claim 4, wherein said receive lock data output means includes: a sixth inverter gate for invert-buffering the output signal from said frequency-dividing means; a P-type Metal-Oxide-Semiconductor (PMOS) transistor having its gate terminal connected to an output terminal of said sixth inverter gate and its source terminal connected to a power source terminal; and a N-type Metal-Oxide-Semiconductor (NMOS) transistor having its gate and source terminals connected to ground and its drain terminal connected to a drain terminal of said PMOS transistor, both the drain terminals forming a receive lock data output terminal at a junction therebetween.