System for modulating/demodulating digital signals transmitted with encoded modulation

Claim 3

The system according to claim 1, wherein said first efficiency equals 6/7, said second efficiency equals 7/8 and said third efficiency equals 3/4.

Claim 4

System according to claim 1, characterised in that the convolutive encoder encodes input bits X i (i=1 to 7) with output bits Y j (j=1 to 8) such that the bits X 3 , X 4 , X 5 , X 6 , X 7 become, without encoding, the bits Y 2 , Y 5 , Y 6 , Y 7 , Y 8 respectively, the remaining output bits being encoded by the convolutive encoder which comprises: a first delay-operator operating on X 2 a second delay-operator operating on X 1 a third delay-operator operating on X 1 delayed a first exclusive OR gate which receives: X 3 , X 2 and X 2 delayed a second exclusive OR gate which receives: X 2 delayed, X 1 and X 1 delayed twice, and which delivers Y 1 an AND gate which receives X 1 delayed once and the output from the second exclusive OR gate a third exclusive OR gate which receives the outputs from the first exclusive OR gate and from the AND gate and which delivers Y 4 a fourth exclusive OR gate which receives the outputs from the second exclusive OR gate and from the second delay-operator and which delivers Y 3 .

Claim 5

System according to claim 1, characterised in that the second encoder comprises, ahead of the convolutive encoder, a differential encoder which sets up rotational invariance.

Claim 6

System according to claim 4, characterised in that the differential encoder encodes input bits IX i (i=1 to 7) with output bits X i (i=1 to 7) such that the bits IX 4 , IX 5 , IX 6 , IX 7 become, without encoding, the bits X 4 , X 5 , X 6 , X 7 respectively, the remaining output bits being encoded by the differential encoder which comprises: a fourth delay-operator operating on Y 1 followed by an inverter a fifth delay-operator operating on the output X 3 a sixth delay-operator operating on X 2 another AND gate which receives Y 1 and the output from the inverter a fifth exclusive OR gate which receives the output from another AND gate 86, the output from the fifth delay-operator and the input IX 3 and which delivers the encoded bit X 3 a sixth exclusive OR gate which receives the output from the sixth delay-operator and the input IX 2 , and which delivers the encoded bit X 2 .

Claim 7

A system according to claim 1, characterised in that the binary allocation module executes the binary allocation of characters of a constellation according to the following correspondence table, with I and Q representing the phase and quadrature components respectively of the signals representing the characters of the constellation and the binary allocation representing the binary values allocated to I and Q respectively, said binary values being separated by commas: ______________________________________ I Q binary allocation ______________________________________ subset C.sub.0 1 1 00,00 1 -3 01,00 -3 1 11,00 -3 -3 10,00 subset C.sub.1 -1 1 00,01 -1 -3 11,01 3 1 01,01 3 -3 10,01 subset C.sub.2 -1 -1 00,10 -1 3 01,10 3 -1 11,10 3 3 10,10 subset C.sub.3 1 -1 00,11 1 3 11,11 -3 -1 01,11 -3 3 10,11 ______________________________________

Claim 8

System according to claim 1, characterised in that the binary redundancy is distributed over two characters emanating respectively from two multiplexed 16 QAMs.

Claim 9

System according to claim 1, characterised in that the first encoder comprises, in series, a Reed-Solomon encoder RS1, an interlacer 1, a Reed-Solomon encoder RS2 and an interlacer 2.