US5307372A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Radio transceiver for transmitting and receiving data packets
Assignee: McKesson Information Solutions LLC
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Filing: 1992-12-15
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Granted: 1994-04-26
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Expires: 2012-12-15
Abstract
Abstract An apparatus for transmitting and receiving packets of data among a multitude of base and remote units utilizing a frequency hopping technique. The apparatus uses a single clock source for synchronizing the analog signal processing circuit, the modular encoder and the micrprocessor, and uses an inexpensive microprocessor with a serial peripheral interface.
Inventors
- 👤 Jonathan F. Sawyer
- 👤 Dennis J. Gardner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:44
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/69; H04B1/713; H04B1/7136; A; A61; A61B; A61B5/00; A61B5/41; A61B5/411; G; G06; G06F; G06F1/00; G06F1/16; G06F1/1613; G06F1/1626; G06F1/1633; G06F1/1684; G06F1/1698; G06K; G06K17/00; G06K7/00; G06K7/10; G06K7/10544; G06K7/10821; G06K7/10881; G07; G07C; G07C9/00; G07C9/20; G07C9/27; G07C9/28; H04B1/7156; G06F2200/00; G06F2200/16; G06F2200/163; G06F2200/1633; H04B2001/71365
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
67 words
A frequency-hopped packet radio transceiver, comprising: an analog signal processing circuit; a modular encoder in electrical communication with the analog signal processing circuit for encoding signals for transmission from the transceiver; a microprocessor in electrical communication with the analog signal processing circuit for processing signals; and a clock, the clock being in electrical communication with and for synchronizing the analog signal processing circuit and the modular encoder.
Claim 2
Dependent Claim
67 words
A frequency-hopped packet radio transceiver, comprising: an analog signal processing circuit; a modular encoder in electrical communication with the analog signal processing circuit for encoding signals for transmission from the transceiver; a microprocessor in electrical communication with the analog signal processing circuit for processing signals; and a clock, the clock being in electrical communication with and for synchronizing the analog signal processing circuit and the modular encoder.
Claim 3
Dependent Claim
25 words
The transceiver of claim 1, wherein the analog signal processing circuit includes an oscillator and an intermediate frequency amplifier, in operative communication with said clock.
Claim 4
Dependent Claim
13 words
The transceiver of claim 2, wherein the clock is a 9.8 MHz clock.
Claim 5
Dependent Claim
26 words
The transceiver of claim 1, wherein the microprocessor includes a serial peripheral interface with a shift register, a read buffer and a high speed data bus.
Claim 6
Dependent Claim
37 words
The transceiver of claim 4, wherein the microprocessor is programmed to move data from the shift register to the high speed data bus at least a byte at a time by accumulating bits in the shift register.
Claim 7
Dependent Claim
20 words
The transceiver of claim 5, wherein the microprocessor uses a duty cycle clocking signal that is narrower than one bit.
Claim 8
Dependent Claim
34 words
The transceiver of claim 6, wherein the microprocessor has a latch that which deactivates upon the reception of a byte of a predetermined bit sequence, whereby the microprocessor is synchronized with a transmitting device.
Claim 9
Dependent Claim
34 words
The transceiver of claim 1, wherein the analog signal processing circuit includes a phase lock loop to switch to and maintain a signal in one of a plurality of predetermined transmission and receiving channels.
Claim 10
Dependent Claim
38 words
The transceiver of claim 1, wherein the modular encoder encodes signals with a code including a +1, a -1 and a 0, whereby the +1 and -1 correspond to 1 bits and the 0 corresponds to 0 bits.
Claim 11
Independent Claim
68 words
A method for frequency-hopped packet transmitting, receiving and processing radio signals, comprising: designating a first station; designating a second station having a microprocessor, an analog signal processing unit, a modular encoder and a clock; synchronizing the microprocessor, analog signal processing unit and modular encoder utilizing said clock; synchronizing said first station with said second station; and transmitting and receiving signals between said first station and said second station.
Claim 12
Independent Claim
68 words
A method for frequency-hopped packet transmitting, receiving and processing radio signals, comprising: designating a first station; designating a second station having a microprocessor, an analog signal processing unit, a modular encoder and a clock; synchronizing the microprocessor, analog signal processing unit and modular encoder utilizing said clock; synchronizing said first station with said second station; and transmitting and receiving signals between said first station and said second station.
Claim 13
Dependent Claim
36 words
The method of claim 10, wherein said synchronizing step includes transmitting a predetermined synchronization bit sequence from one of said first station and said second station to the other of said first station and second station.
Claim 14
Dependent Claim
36 words
The method of claim 10, further comprising encoding the transmitted signals in a code including a +1, a -1 and a 0, so that the DC and low frequency components of the bit stream are minimized.
Claim 15
Dependent Claim
48 words
The method of claim 10, wherein the microprocessor includes a serial peripheral interface with a shift register, a read buffer and a high speed data bus, and bit signals are accumulated in the shift register and moved to the data bus at least a byte at a time.
Claim 16
Dependent Claim
35 words
The method of claim 13, wherein the microprocessor duty cycle clock is narrower than one bit, so that the signals are transmitted from the shift register to the data bus in less than a bit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-25 | 1997-10-25 | 1998-04-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-25 | 2001-10-25 | 2002-04-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-25 | 2005-10-25 | 2006-04-26 | $7700.00 | Window Closed / Lapsed |