US5303261A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-throughput pipelined communication channel for interruptible data transmission
Assignee: Lockheed Martin Corp
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Filing: 1991-11-29
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Granted: 1994-04-12
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Expires: 2011-11-29
Abstract
Abstract A high-throughput bidirectional data communication channel is formed of a pipelined plurality M of stages, connected to the input/output (I/O) port of each of the pair of devices using the channel, and configured to allow interruptibility of data transmission by either device connected to the channel; either device may be sender or receiver and transmission of data may be interrupted by either device for any number of cycles and resumed without loss or duplication of data at the receiver. The channel uses pipelining to achieve longer distance parallel transmission of N plural data bits, while maintaining the maximum high speed throughput. The channel, and its associated data transfer protocol, supports bidirectional transmission of data between the two sourcing/terminating devices with maximum throughput being achieved by transmitting a word of parallel data during every clock cycle.
Inventors
- 👤 Michael F. Junod
- 👤 Edward J. Monastra
- 👤 Chaim Strasberg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 00:18
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/14; G; G06; G06F; G06F5/00; G06F5/06; G06F5/065; H04L5/00; H04L5/14
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
128 words
Communications channel apparatus for digital data transfer between first and second spaced-apart devices in a system, comprising: clock means for providing a periodic transfer signal; and a plurality M of pipeline transfer stages, through which said data is sequentially transferred between a data I/O port of a sending one of said devices and a data I/O port of a receiving one of said devices; each of said transfer stages having register means for temporarily storing all bits of a N-bit-wide word of parallel data input for transfer, responsive to a first clock signal, and then transferring all of the stored data bits, responsive to a next clock signal, to a next one of a subsequent stage and the receiving device, if no further stages exist in the pipeline.
Claim 2
Dependent Claim
128 words
Communications channel apparatus for digital data transfer between first and second spaced-apart devices in a system, comprising: clock means for providing a periodic transfer signal; and a plurality M of pipeline transfer stages, through which said data is sequentially transferred between a data I/O port of a sending one of said devices and a data I/O port of a receiving one of said devices; each of said transfer stages having register means for temporarily storing all bits of a N-bit-wide word of parallel data input for transfer, responsive to a first clock signal, and then transferring all of the stored data bits, responsive to a next clock signal, to a next one of a subsequent stage and the receiving device, if no further stages exist in the pipeline.
Claim 3
Dependent Claim
55 words
The communications channel of claim 1, wherein each device sources both a data-ready-for-transfer RDY signal and a data-direction DIR signal to the channel for transmission to the other device, with the readiness of the device to respectively transmit and receive data being determined by the associated one of opposite data states of the DIR signal.
Claim 4
Dependent Claim
32 words
The communications channel of claim 2, wherein each pipeline stage includes register means for temporarily storing and then transferring each of the DIR and RDY signals from each of the two devices.
Claim 5
Dependent Claim
30 words
The communications channel of claim 3, wherein each stage includes four independent register means, each configured to store and subsequently transmit a different one of the DIR and RDY signals.
Claim 6
Dependent Claim
45 words
The communications channel of claim 4, wherein the direction of data travel through the channel is established by that one of the DIR signal first at a selected state contemporaneous with the presence of the RDY signal from the same device at another selected state.
Claim 7
Dependent Claim
16 words
The communications channel of claim 5, wherein either device can interrupt data transmission through the channel.
Claim 8
Dependent Claim
22 words
The communications channel of claim 6, wherein the N data storage means of each pipeline stage are configured for bidirectional data transfer.
Claim 9
Dependent Claim
49 words
The communications channel of claim 2, wherein the direction of data transfer through the N stages of the channel is established by that one of the DIR signal first at a selected state contemporaneous with the presence of the RDY signal from the same device at another selected state.
Claim 10
Dependent Claim
30 words
The communications channel of claim 1, wherein each device has input queue means each containing a pipeline of up to 2M sequential, clocked register means for receiving the channel information.
Claim 11
Dependent Claim
214 words
Communications channel apparatus for digital data transfer between first and second spaced-apart devices in a system, with each device sourcing both a data-ready-for-transfer RDY signal and a data-direction DIR signal to the channel for transmission to the other device, comprising: clock means for providing a periodic transfer signal; and a plurality M of pipeline transfer stages, through which said data is sequentially transferred between a data I/O port of a sending one of said devices and a data I/O port of a receiving one of said devices, with the direction of data travel through the channel being established by that one of the DIR signal first at a selected state contemporaneous with the presence of the RDY signal from the same device at another selected state; each of said transfer stages having four independent register means, each configured for temporarily storing and then transferring each of the DIR and RDY signals from each of the two devices and also having register means for temporarily storing a N-bit-wide word of parallel data input for transfer, responsive to a first clock signal, and then transferring the stored signals and data, responsive to a next clock signal, to a next one of a subsequent stage and the receiving device, if no further stages exist in the pipeline.
Claim 12
Dependent Claim
214 words
Communications channel apparatus for digital data transfer between first and second spaced-apart devices in a system, with each device sourcing both a data-ready-for-transfer RDY signal and a data-direction DIR signal to the channel for transmission to the other device, comprising: clock means for providing a periodic transfer signal; and a plurality M of pipeline transfer stages, through which said data is sequentially transferred between a data I/O port of a sending one of said devices and a data I/O port of a receiving one of said devices, with the direction of data travel through the channel being established by that one of the DIR signal first at a selected state contemporaneous with the presence of the RDY signal from the same device at another selected state; each of said transfer stages having four independent register means, each configured for temporarily storing and then transferring each of the DIR and RDY signals from each of the two devices and also having register means for temporarily storing a N-bit-wide word of parallel data input for transfer, responsive to a first clock signal, and then transferring the stored signals and data, responsive to a next clock signal, to a next one of a subsequent stage and the receiving device, if no further stages exist in the pipeline.
Claim 13
Dependent Claim
16 words
The communications channel of claim 10, wherein either device can interrupt data transmission through the channel.
Claim 14
Dependent Claim
22 words
The communications channel of claim 11, wherein the N data storage means of each pipeline stage are configured for bidirectional data transfer.
Claim 15
Dependent Claim
22 words
The communications channel of claim 10, wherein the N data storage means of each pipeline stage are configured for bidirectional data transfer.
Claim 16
Dependent Claim
30 words
The communications channel of claim 10, wherein each device has input queue means each containing a pipeline of up to 2M sequential, clocked register means for receiving the channel information.
Claim 17
Dependent Claim
189 words
Communications channel apparatus for digital data transfer between first and second spaced-apart devices in a system, with each device sourcing both a data-ready-for-transfer RDY signal and a data-direction DIR signal to the channel for transmission to the other device, comprising: clock means for providing a periodic transfer signal; and a plurality M of pipeline transfer stages, through which said data is sequentially transferred between a data I/O port of a sending one of said devices and a data I/O port of a receiving one of said devices; each of said transfer stages having register means for temporarily storing a N-bit-wide word of parallel data input for transfer, responsive to a first clock signal, and then transferring the stored data, responsive to a next clock signal, to a next one of a subsequent stage and the receiving device, if no further stages exist in the pipeline; and wherein the direction of data transfer through the N stages of the channel is established by that one of the DIR signals first at a selected state contemporaneous with the presence of the RDY signal from the same device at another selected state.
Claim 18
Dependent Claim
189 words
Communications channel apparatus for digital data transfer between first and second spaced-apart devices in a system, with each device sourcing both a data-ready-for-transfer RDY signal and a data-direction DIR signal to the channel for transmission to the other device, comprising: clock means for providing a periodic transfer signal; and a plurality M of pipeline transfer stages, through which said data is sequentially transferred between a data I/O port of a sending one of said devices and a data I/O port of a receiving one of said devices; each of said transfer stages having register means for temporarily storing a N-bit-wide word of parallel data input for transfer, responsive to a first clock signal, and then transferring the stored data, responsive to a next clock signal, to a next one of a subsequent stage and the receiving device, if no further stages exist in the pipeline; and wherein the direction of data transfer through the N stages of the channel is established by that one of the DIR signals first at a selected state contemporaneous with the presence of the RDY signal from the same device at another selected state.
Claim 19
Dependent Claim
32 words
The communications channel of claim 15, wherein each pipeline stage includes register means for temporarily storing and then transferring each of the DIR and RDY signals from each of the two devices.
Claim 20
Dependent Claim
45 words
The communications channel of claim 15, wherein the direction of data travel through the channel is established by that one of the DIR signal first at a selected state contemporaneous with the presence of the RDY signal from the same device at another selected state.
Claim 21
Dependent Claim
22 words
The communications channel of claim 15, wherein the N data storage means of each pipeline stage are configured for bidirectional data transfer.
Claim 22
Dependent Claim
30 words
The communications channel of claim 15, wherein each device has input queue means each containing a pipeline of up to 2M sequential, clocked register means for receiving the channel information.
References Cited (Backward Citations)
US4159535A
Cited
US4571671A
Cited
US4577327A
Cited
US5113418A
Cited
US4945548A
Cited
US5132987A
Cited
US5081646A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-11 | 1997-10-11 | 1998-04-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-11 | 2001-10-11 | 2002-04-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-11 | 2005-10-11 | 2006-04-12 | $7700.00 | Window Closed / Lapsed |