US5303183A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Mitsubishi Electric Corp
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Filing: 1991-05-29
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Granted: 1994-04-12
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Expires: 2011-05-29
Abstract
Abstract In the case where information is read from a selected memory cell, the transfer gate included in the memory cell is turned on, and one electrode of the memory cell capacitor is connected to one bit line of a corresponding bit line pair. At the same time, the other electrode of the memory cell capacitor, i.e. the cell plate electrode is connected to the other bit line of the corresponding bit line pair. As a result, a change of the potentials occur at both the bit lines of the corresponding bit line pair. This change of the potentials acts in the different directions between one bit line and the other bit line. Therefore, the read potential difference appearing on the bit line pair becomes larger, and malfunction of the sense amplifier is reduced, while the incidence of soft error can be reduced.
Inventors
- 👤 Mikio Asakura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:02
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074; G11C11/403; G11C11/404
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
248 words
A semiconductor memory device, comprising: a plurality of word lines, and a plurality of bit lines crossing said word lines and arranged as complementary bit line pairs, a plurality of memory cells arranged at respective crossings of said word lines and said bit lines, a plurality of cell plate lines corresponding, respectively, to said bit line pairs, each said memory cell comprising a transfer means and a capacitor for storing an information charge, the capacitor of each memory cell having a first plate connected, through corresponding said transfer means, to one bit line of a corresponding bit line pair and a second plate connected to the corresponding cell plate line, first and second switches connected, respectively, between said cell plate line and said first bit line and between said cell plate line and said second bit line of each bit line pair, each of said first and second switches being common to a plurality of memory cells connected to each bit line pair; and selector means for selecting a word line and a bit line corresponding to a particular memory cell, transfer control means responsive to said selecting means for controlling the transfer means of the particular memory cell on one of said first and second bit lines of a selected bit line pair; and switch control means for controlling said first and second switches to connect said cell plate line to the other one of said first and second bit lines of said selected bit line pair.
Claim 2
Dependent Claim
248 words
A semiconductor memory device, comprising: a plurality of word lines, and a plurality of bit lines crossing said word lines and arranged as complementary bit line pairs, a plurality of memory cells arranged at respective crossings of said word lines and said bit lines, a plurality of cell plate lines corresponding, respectively, to said bit line pairs, each said memory cell comprising a transfer means and a capacitor for storing an information charge, the capacitor of each memory cell having a first plate connected, through corresponding said transfer means, to one bit line of a corresponding bit line pair and a second plate connected to the corresponding cell plate line, first and second switches connected, respectively, between said cell plate line and said first bit line and between said cell plate line and said second bit line of each bit line pair, each of said first and second switches being common to a plurality of memory cells connected to each bit line pair; and selector means for selecting a word line and a bit line corresponding to a particular memory cell, transfer control means responsive to said selecting means for controlling the transfer means of the particular memory cell on one of said first and second bit lines of a selected bit line pair; and switch control means for controlling said first and second switches to connect said cell plate line to the other one of said first and second bit lines of said selected bit line pair.
Claim 3
Dependent Claim
29 words
The semiconductor memory device according to claim 1 further comprising: means for precharging each of said bit lines and each of said cell plate lines to the same potential.
Claim 4
Dependent Claim
44 words
The semiconductor memory device according to claim 2 further comprising: a plurality of sense amplifier means, each provided to each of said bit line pairs, for amplifying the potential difference between said first and second bit lines of the corresponding bit line pairs, respectively.
Claim 5
Dependent Claim
24 words
A semiconductor memory device according to claim 3 further comprising: sense amplifier control means for controlling activation/inactivation of each of said sense amplifier means.
Claim 6
Dependent Claim
30 words
A semiconductor memory device according to claim 4, wherein said sense amplifier control means activates each of said sense amplifiers after said switch control means has ended its control operation.
Claim 7
Dependent Claim
34 words
A semiconductor memory device according to claim 4 further comprising: means for electrically disconnecting each of said bit lines and each of said sense amplifier means after said switch means starts its control operation.
Claim 8
Dependent Claim
29 words
A semiconductor memory device according to claim 6 further comprising: said sense amplifier control means activates each of said sense amplifier before said switch means ends its control operation.
Claim 9
Dependent Claim
21 words
A semiconductor memory device according to claim 1, wherein each of said bit line pair has a folded bit line structure.
Claim 10
Dependent Claim
21 words
A semiconductor memory device according to claim 1, wherein each of said bit line pairs has an open bit line structure.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-11 | 1997-10-11 | 1998-04-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-11 | 2001-10-11 | 2002-04-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-11 | 2005-10-11 | 2006-04-12 | $7700.00 | Window Closed / Lapsed |