Double unequal bus timeout

Claim 2

In a computer system including a plurality of devices coupled to a system bus, each device of the plurality of devices capable of operating as either an initiator or a target device, each device comprising: (a) timing means for keeping elapsed time such that: (i) if the device operates as an initiator, the timing means keeps elapsed time responsive to the device operating as an initiator, and issues a first timeout signal if a first predetermined time period of the timer has elapsed; and (ii) if the device operates as a target, the timing means keeps elapsed time responsive to the device being operated as a target, and issues a second timeout signal if a second predetermined time period has elapsed; (b) a bus monitor, coupled to the bus and the timing means, for asserting control of the bus responsive to the device operating as a target and for de-asserting control if the timing means issues the second timeout signal; and (c) a reset control, coupled to the timing means and the bus, for receiving a timeout signal and responding to it by issuing a reset signal on the bus if the timeout signal received is the first timeout signal; such that, by issuing a reset signal or by de-asserting control of the bus, the bus is placed in condition for one of the plurality of devices to obtain control of the bus.

Claim 3

The device of claim 1 wherein the second timeout signal is issued from the timing means to the reset control which directs the bus monitor to de-assert control of the bus.

Claim 4

The device of claim 1 further comprising a peripheral storage unit.

Claim 5

The device of claim 1 wherein the device further comprises one or more resettable elements coupled to the reset control and wherein the reset control detects a reset signal placed on the bus by another device and resets one or more of the resettable elements in response to detecting the reset signal.

Claim 6

The device of claim 4 wherein one or more of the resettable elements comprises a state machine.

Claim 7

The device of claim 1 wherein the device further comprises one or more resettable elements coupled to the reset control and wherein the reset control resets one or more of the resettable elements in response to receiving a timeout signal from the timing means.

Claim 8

The device of claim 6 wherein one or more of the resettable elements comprises a state machine.

Claim 9

The device of claim 1 wherein the bus monitor de-asserts control of the bus in response to a reset signal received from the bus.

Claim 10

The device of claim 8 wherein the reset signal is received by the reset control which directs the bus monitor to de-assert control of the bus.

Claim 11

The device of claim 1 wherein the second predetermined time period is less than the first predetermined time period.

Claim 12

A computer system including a plurality of devices coupled to a system bus, each device of the plurality of devices capable of operating as either an initiator or a target device, the system comprising: (a) a first device, the first device comprising: (i) first device timing means for keeping elapsed time responsive to the first device operating as an initiator and for issuing a first timeout signal if a first predetermined time period has elapsed; and (ii) a reset control, coupled to the first device timing means and the bus, for receiving the first timeout signal and responding to it by issuing a reset signal on the bus; and (b) a second device, the second device comprising: (i) second device timing means for keeping elapsed time responsive to the second device operating as a target and for issuing a second timeout signal if a second predetermined time period has elapsed; and (ii) a bus monitor, coupled to the bus and the second device timing means, for asserting control of the bus responsive to the second device operating as a target and for de-asserting control if the second device timing means issues a second timeout signal; such that, by the first device issuing a reset signal or the second device de-asserting control of the bus, the bus is placed in condition for one device of the plurality of devices to obtain control of the bus.

Claim 13

A computer system including a plurality of devices coupled to a system bus, each device of the plurality of devices capable of operating as either an initiator or a target device, the system comprising: (a) a first device, the first device comprising: (i) first device timing means for keeping elapsed time responsive to the first device operating as an initiator and for issuing a first timeout signal if a first predetermined time period has elapsed; and (ii) a reset control, coupled to the first device timing means and the bus, for receiving the first timeout signal and responding to it by issuing a reset signal on the bus; and (b) a second device, the second device comprising: (i) second device timing means for keeping elapsed time responsive to the second device operating as a target and for issuing a second timeout signal if a second predetermined time period has elapsed; and (ii) a bus monitor, coupled to the bus and the second device timing means, for asserting control of the bus responsive to the second device operating as a target and for de-asserting control if the second device timing means issues a second timeout signal; such that, by the first device issuing a reset signal or the second device de-asserting control of the bus, the bus is placed in condition for one device of the plurality of devices to obtain control of the bus.

Claim 14

The system of claim 11 wherein the first device further comprises one or more resettable elements coupled to the reset control and wherein the reset control detects a reset signal placed on the bus by another device and resets one or more of the resettable elements in response to detecting the reset signal.

Claim 15

The system of claim 11 wherein the first device further comprises one or more resettable elements coupled to the reset control and wherein the reset control resets one or more of the resettable elements in response to receiving a first timeout signal from the first device timing means.

Claim 16

The system of claim 11 wherein the second device further comprises a second device reset control, coupled to the second device timing means and the bus, for receiving the second timeout signal and responding to it by issuing a reset signal on the bus.

Claim 17

The system of claim 11 wherein the second device further comprises a second device reset control, coupled to the second device timing means and the bus monitor, for receiving the second timeout signal and directing the bus monitor to de-assert control of the bus.

Claim 18

The system of claim 11 wherein the second device further comprises one or more resettable elements and a second device reset control, coupled to the one or more resettable elements and the bus, wherein the second device reset control resets one or more of the resettable elements in response to receiving a reset signal from the bus.

Claim 19

The system of claim 11 wherein the second device further comprises one or more resettable elements and a second device reset control, coupled to the second device timing means and the one or more resettable elements, wherein the second device reset control resets one or more of the resettable elements in response to receiving a second timeout signal from the second timing means.

Claim 20

The system of claim 11 wherein the bus monitor of the second device de-asserts control of the bus in response to a reset signal received from the bus.

Claim 21

The system of claim 18 wherein the second device further comprises a second device reset control, coupled to the bus monitor and the bus, for receiving a reset signal from the bus and directing the bus monitor to de-assert control of the bus.

Claim 22

The device of claim 11 wherein the second predetermined time period is less than the first predetermined time period.