Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
266 words
An apparatus for converting N picture elements (pels) of an image to an M pel scaled representation of said image, where N and M are each integers greater than 0, the combination comprising: a first register for storing -N; a second register for storing M; a third register for storing a sum (S), wherein initially S=M-N; a discriminator, which is responsive to S, for generating a first signal when S is not negative, and for generating a second signal when S is negative; an adder for adding the value of S stored in said third register with -N in response to said first signal, and for adding the value of S stored in said first signal, and for adding the value of S stored in said third register with M in response to said signal, for in each instance providing a new S for storage in said third register; a first address counter which is incremented by said first signal; a second address counter which is incremented by said second signal; an input buffer including N member positions for storing N pels of said image; an output buffer including M memory positions, with each of said M memory positions initially being set to 0; and means responsive to said first signal and to incremented count of said first address counter and to incremented count of said second address counter and for transferring at least one of said N pels from said input buffer to at least one of said M pel positions of said output buffer to form said M pel scaled representation of said image.
Claim 2
Independent Claim
266 words
An apparatus for converting N picture elements (pels) of an image to an M pel scaled representation of said image, where N and M are each integers greater than 0, the combination comprising: a first register for storing -N; a second register for storing M; a third register for storing a sum (S), wherein initially S=M-N; a discriminator, which is responsive to S, for generating a first signal when S is not negative, and for generating a second signal when S is negative; an adder for adding the value of S stored in said third register with -N in response to said first signal, and for adding the value of S stored in said first signal, and for adding the value of S stored in said third register with M in response to said signal, for in each instance providing a new S for storage in said third register; a first address counter which is incremented by said first signal; a second address counter which is incremented by said second signal; an input buffer including N member positions for storing N pels of said image; an output buffer including M memory positions, with each of said M memory positions initially being set to 0; and means responsive to said first signal and to incremented count of said first address counter and to incremented count of said second address counter and for transferring at least one of said N pels from said input buffer to at least one of said M pel positions of said output buffer to form said M pel scaled representation of said image.
Claim 3
Independent Claim
282 words
An apparatus for converging N picture elements (pels) of an image to an M pel scaled representation of said image, where N and M are each integers greater than 0, the combination comprising: a first register for storing -N; a second register for storing M; a third register for storing a sum (S), wherein initially S=M-N; a discriminator, which is responsive to S, for generating a first signal when S is not negative, and for generating a second signal when S is negative; an adder for adding the value of S stored in said third register with =N in response to said first signal, and for adding the value of S stored in said first signal, and for adding the value of S stored in said third register with M in response to said signal, for in each instance providing a new S for storage in said third register; an input buffer including N memory positions for storing N pels of said image; an output buffer including M memory positions, with each of said M memory positions initially being set to 0; a first address counter which is incremented by said first signal to point at a given addressed memory position of said input buffer in response to being incremented; a second address counter which is incremented by said second signal to point at a given addressed memory position of said output buffer in response to being incremented; and means responsive to said first signal to store said pel data, from an address memory position of said input buffer pointed to by said second address counter, to an addressed memory position of said output buffer pointed to by said first address counter.
Claim 4
Independent Claim
282 words
An apparatus for converging N picture elements (pels) of an image to an M pel scaled representation of said image, where N and M are each integers greater than 0, the combination comprising: a first register for storing -N; a second register for storing M; a third register for storing a sum (S), wherein initially S=M-N; a discriminator, which is responsive to S, for generating a first signal when S is not negative, and for generating a second signal when S is negative; an adder for adding the value of S stored in said third register with =N in response to said first signal, and for adding the value of S stored in said first signal, and for adding the value of S stored in said third register with M in response to said signal, for in each instance providing a new S for storage in said third register; an input buffer including N memory positions for storing N pels of said image; an output buffer including M memory positions, with each of said M memory positions initially being set to 0; a first address counter which is incremented by said first signal to point at a given addressed memory position of said input buffer in response to being incremented; a second address counter which is incremented by said second signal to point at a given addressed memory position of said output buffer in response to being incremented; and means responsive to said first signal to store said pel data, from an address memory position of said input buffer pointed to by said second address counter, to an addressed memory position of said output buffer pointed to by said first address counter.