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US5301085A Expired / Lapsed US ⏱️ 0.0 years remaining

Control circuit for a semiconductor switch

Assignee: ABB Stromberg Drives Oy
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Filing: 1992-12-09
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Granted: 1994-04-05
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Expires: 2012-12-09
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Abstract

Abstract The invention relates to a semiconductor switch control circuit comprising a timing logic unit (1), a first and a second driver (2, 3) controlled by the timing logic unit, a first and a second transformer (T1, T2), to which the first and the second driver (2, 3), respectively, apply an unmodulated ac voltage signal (A, B) for bringing the semiconductor switch into a conducting and non-conducting state, respectively, and the secondary windings of which are connected at the opposite ends to a reference potential (RP); a first and a second rectifier (4, 5) for rectifying dc voltages (V+, V-) of opposite polarity from a voltage (A, B) acting across the secondary windings of the transformers; a first and a second driver (10, 11) for maintaining the semiconductor switch (12) in a conducting and non-conducting state, respectively; and capacitor units (8, 9) for storing the turn-on and turn-off energy of the semiconductor switch, respectively.

Inventors

  • 👤 Erkki Miettinen

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 00:00
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/689; H03K17/691

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 333 words
A control circuit for a semiconductor switch, comprising a control unit (1 to 3) and a transformer (T1, T2) connected to it for generating an ac voltage signal (A, B) in the secondary winding of the transformer, the ac voltage signal containing control information and control energy for the semiconductor switch (12); a rectifier (4, 5) connected to the secondary winding of the transformer (T1, T2) for generating a dc voltage (V+, V-) for controlling the semiconductor switch; a logic circuit (6) for separating the control information contained in the secondary voltage of the transformer from the secondary voltage, and a driver (10, 11) controlled by the logic circuit (6) for controlling the semiconductor switch (12), the emitter electrode of the semiconductor switch being connected to a reference potential (RP), c h a r a c t e r i z e d in that the control unit comprises a timing logic unit (1) and a first and a second driver (2, 3) controlled by the timing logic unit (1), and the transformer comprises a first and a second transformer (T1, T2), to which the first and the second driver (2, 3), respectively, applies an unmodulated ac voltage signal (A, B) for bringing the semiconductor switch into a conducting and non-conducting state, respectively, and the secondary windings of which are connected at their opposite ends to said reference potential (RP); the rectifier comprises a first and a second rectifier (4, 5) for rectifying a positive dc voltage (V+) and a negative dc voltage (V-) with respect to the reference potential, respectively, from the voltage (A, B) acting across the secondary windings of the transformers; the driver controlled by the logic circuit (6) comprises a first and a second driver (10, 11) for maintaining the semiconductor switch in a conducting and non-conducting state, respectively; and that the control circuit further comprises capacitor units (8, 9) connected to the outputs of the rectifiers for storing the turn-on and turn-off energy of the semiconductor switch, respectively.
Claim 2
Dependent Claim 333 words
A control circuit for a semiconductor switch, comprising a control unit (1 to 3) and a transformer (T1, T2) connected to it for generating an ac voltage signal (A, B) in the secondary winding of the transformer, the ac voltage signal containing control information and control energy for the semiconductor switch (12); a rectifier (4, 5) connected to the secondary winding of the transformer (T1, T2) for generating a dc voltage (V+, V-) for controlling the semiconductor switch; a logic circuit (6) for separating the control information contained in the secondary voltage of the transformer from the secondary voltage, and a driver (10, 11) controlled by the logic circuit (6) for controlling the semiconductor switch (12), the emitter electrode of the semiconductor switch being connected to a reference potential (RP), c h a r a c t e r i z e d in that the control unit comprises a timing logic unit (1) and a first and a second driver (2, 3) controlled by the timing logic unit (1), and the transformer comprises a first and a second transformer (T1, T2), to which the first and the second driver (2, 3), respectively, applies an unmodulated ac voltage signal (A, B) for bringing the semiconductor switch into a conducting and non-conducting state, respectively, and the secondary windings of which are connected at their opposite ends to said reference potential (RP); the rectifier comprises a first and a second rectifier (4, 5) for rectifying a positive dc voltage (V+) and a negative dc voltage (V-) with respect to the reference potential, respectively, from the voltage (A, B) acting across the secondary windings of the transformers; the driver controlled by the logic circuit (6) comprises a first and a second driver (10, 11) for maintaining the semiconductor switch in a conducting and non-conducting state, respectively; and that the control circuit further comprises capacitor units (8, 9) connected to the outputs of the rectifiers for storing the turn-on and turn-off energy of the semiconductor switch, respectively.
Claim 3
Dependent Claim 65 words
A control circuit according to claim 1, c h a r a c t e r i z e d in that it further comprises a short-circuit turn-off driver (7) controlled by the logic circuit (6) for connecting the control electrode of the semiconductor switch (12) to a source of turn-off energy (V-) when a current flowing through the semiconductor switch exceeds a predetermined value.

References Cited (Backward Citations)

US4748532A Cited
JPH0287963A Cited
US5055721A Cited
US5019719A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-04-04 1997-10-04 1998-04-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-04-04 2001-10-04 2002-04-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-04-04 2005-10-04 2006-04-05 $7700.00 Window Closed / Lapsed

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