Line data-block data converting circuit

Claim 1

A converting circuit for converting line data to block data, said block data corresponding to a plurality of pixels, of which only valid pixels are output to a cosine transformation section, said converting circuit being used with a plurality of different system clock frequency modes in NTSC and PAL systems, said converting circuit comprising: a memory having a capacity of at least n×b max pixels where b max is equal to a number of valid pixels in a selected frequency mode providing the largest number of valid pixels for one horizontal period with respect to said plurality of different system clock frequency modes and n×n is equal to the number of pixels in a block; a memory controller having a read only memory (ROM) tabled for storing a plurality of predetermined addresses equal in number to n×b max for n horizontal periods; the memory controller being constructed such that data of n×b valid pixels are stored in said n×b max addresses in the memory in n horizontal periods when line data in a frequency mode other than said selected frequency mode are stored in the memory and the number of valid pixels for one horizontal period in said frequency mode other than the selected frequency mode is equal to b; the memory controller also being constructed such that data of invalid pixels are stored in the memory at a remaining (n×b max )-(n×b) addresses of said n×b max addresses; and means for inhibiting block data corresponding to data of said invalid pixels from being output to said cosine transformation section upon reading of data stored in said memory.