Examination circuit for a sensor

Claim 1

Monitoring circuit for a sensor comprising a high-potential line and a low-potential line, each of said lines being connected to said sensor; an offset voltage source (U -- OS) connected to the low-potential line and producing an offset voltage relative to ground higher than a minimum transistor control voltage; a pulldown resistor connected between said high-potential line and said ground; a first testing transistor having a control electrode connected via a resistor arrangement with said high-potential line and said first testing transistor switching to a blocking state when a potential on the high-potential line drops below the minimum transistor control voltage due to one of a short circuit of the sensor to ground and an interruption of said lines; a second testing transistor having a control electrode connected with said low-potential line via another resistor arrangement and switching to a blocking state when the low-potential line is grounded as a result of a short circuit to ground; and a third testing transistor having a control electrode and a p-type transistor having a control electrode and an output connected with the control electrode of the third testing transistor, said control electrode of the p-type transistor being connected with one of said lines so that said p-type transistor is in a blocking state when said lines have a potential corresponding at least to a potential of an electron receiving electrode relative to the minimum control voltage, so that said third testing transistor enters a blocking state; wherein said three testing transistors have switching states and a combination of said switching states indicate one of a plurality of operating states of said sensor, said operating states including short circuit to ground, short circuit to supply voltage, normal operation and line interruption.