US5291433A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory with leak-resistant bit lines
Assignee: Lapis Semiconductor Co Ltd
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Filing: 1992-09-11
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Granted: 1994-03-01
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Expires: 2012-09-11
Abstract
Abstract Each of the bit lines of a semiconductor memory has an intermediate section with low electrical resistance and low electromigration resistance. If the bit line is shorted to a word line, during burn-in the electrical resistance of the intermediate section increases because of electromigration, thereby preventing excess current from leaking through the shorted bit line during subsequent use.
Inventors
- 👤 Hideki Itoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 19:29
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; G; G11; G11C; G11C5/00; G11C5/06; G11C5/063; H10B10/00; G01; G01R; G01R31/00; G01R31/28; G01R31/30
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
79 words
A semiconductor memory comprising a plurality of bit lines, a plurality of word lines, and an equalizer for precharging said bit lines to a fixed potential, wherein each of said plurality of bit lines has a first section crossing said word lines, a second section coupled to said first section, and a third section coupled to said second section and said equalizer, and said second section has a lower electromigration resistance than said first section and said third section.
Claim 2
Dependent Claim
79 words
A semiconductor memory comprising a plurality of bit lines, a plurality of word lines, and an equalizer for precharging said bit lines to a fixed potential, wherein each of said plurality of bit lines has a first section crossing said word lines, a second section coupled to said first section, and a third section coupled to said second section and said equalizer, and said second section has a lower electromigration resistance than said first section and said third section.
Claim 3
Dependent Claim
49 words
The memory of claim 1, wherein said first section and said third section comprises a first material having a first electrical resistivity, said second section comprises a second material having a second electrical resistivity, and said second electrical resistivity is equal to or less than said first electrical resistivity.
Claim 4
Dependent Claim
42 words
The memory of claim 1, wherein said first section, said second section, and said third section comprises an aluminum alloy, and said alloy has a smaller crystal grain size in said second section than in said first section and said third section.
Claim 5
Dependent Claim
32 words
The memory of claim 3, wherein said second section has a line width and said aluminum alloy has, in said second section, a crystal grain size not exceeding one-half said line width.
Claim 6
Dependent Claim
39 words
The memory of claim 1, wherein each of said plurality of bit lines comprises a layer of an aluminum alloy and a layer of a different conductive material, and said different conductive material is removed in said second section.
Claim 7
Dependent Claim
34 words
The memory of claim 1, wherein said first section and said third section have a first line width and said second section has a second line width not exceeding one-half said first line width.
Claim 8
Dependent Claim
20 words
The memory of claim 6, wherein said first section, said second section, and said third section comprises an aluminum alloy.
Claim 9
Dependent Claim
139 words
A semiconductor memory comprising a plurality of bit lines, a plurality of word lines, an equalizer for precharging said bit lines to a fixed potential, and a semiconductor substrate having a plurality of mutually isolated lightly-doped n-type areas, wherein each of said plurality of bit lines has: a first part crossing said word lines and making contact with a first one of said plurality of lightly-doped n-type areas; a second part comprising an aluminum alloy, not connected to said first part, but making contact with said first one of said plurality of lightly-doped n-type areas and a second one of said plurality of said lightly-doped n-type areas; and a third part, not connected to said first part or said second part, making contact with said second one of said plurality of lightly-doped n-type areas and coupled to said equalizer.
Claim 10
Dependent Claim
139 words
A semiconductor memory comprising a plurality of bit lines, a plurality of word lines, an equalizer for precharging said bit lines to a fixed potential, and a semiconductor substrate having a plurality of mutually isolated lightly-doped n-type areas, wherein each of said plurality of bit lines has: a first part crossing said word lines and making contact with a first one of said plurality of lightly-doped n-type areas; a second part comprising an aluminum alloy, not connected to said first part, but making contact with said first one of said plurality of lightly-doped n-type areas and a second one of said plurality of said lightly-doped n-type areas; and a third part, not connected to said first part or said second part, making contact with said second one of said plurality of lightly-doped n-type areas and coupled to said equalizer.
Claim 11
Dependent Claim
22 words
The memory of claim 8, wherein said first part and said third part comprise a conductive material other than an aluminum alloy.
Claim 12
Dependent Claim
109 words
A semiconductor memory comprising a plurality of bit lines, a plurality of word lines, an equalizer for precharging said bit lines to a fixed potential, and a semiconductor substrate having a plurality of mutually isolated lightly-doped n-type areas, wherein each of said plurality of bit lines has: a first part crossing said word lines; a second part comprising an aluminum alloy, connected to said first part and making contact with one of said plurality of lightly-doped n-type areas; and a third part, not connected to said first part or said second part, making contact with said one of said plurality of lightly-doped n-type areas and coupled to said equalizer.
Claim 13
Dependent Claim
109 words
A semiconductor memory comprising a plurality of bit lines, a plurality of word lines, an equalizer for precharging said bit lines to a fixed potential, and a semiconductor substrate having a plurality of mutually isolated lightly-doped n-type areas, wherein each of said plurality of bit lines has: a first part crossing said word lines; a second part comprising an aluminum alloy, connected to said first part and making contact with one of said plurality of lightly-doped n-type areas; and a third part, not connected to said first part or said second part, making contact with said one of said plurality of lightly-doped n-type areas and coupled to said equalizer.
Claim 14
Dependent Claim
22 words
The memory of claim 10, wherein said first part and said third part comprise a conductive material other than an aluminum alloy.
Claim 15
Dependent Claim
111 words
A semiconductor memory comprising a plurality of bit lines, a plurality of word lines, an equalizer for precharging said bit lines to a fixed potential, and a semiconductor substrate having a plurality of mutually isolated lightly-doped n-type areas each having a heavily-doped n-type area formed therewithin, wherein each of said plurality of bit lines has: a first part comprising an aluminum alloy, crossing said word lines, and making contact with one of said plurality of lightly-doped n-type areas; and a second part, coupled to said equalizer, not connected to said first part, but making contact with the heavily-doped n-type area formed within said one of said plurality of lightly-doped n-type areas.
Claim 16
Dependent Claim
111 words
A semiconductor memory comprising a plurality of bit lines, a plurality of word lines, an equalizer for precharging said bit lines to a fixed potential, and a semiconductor substrate having a plurality of mutually isolated lightly-doped n-type areas each having a heavily-doped n-type area formed therewithin, wherein each of said plurality of bit lines has: a first part comprising an aluminum alloy, crossing said word lines, and making contact with one of said plurality of lightly-doped n-type areas; and a second part, coupled to said equalizer, not connected to said first part, but making contact with the heavily-doped n-type area formed within said one of said plurality of lightly-doped n-type areas.
Claim 17
Dependent Claim
13 words
The memory of claim 12, wherein said second part comprises an aluminum alloy.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-02-28 | 1997-08-30 | 1998-03-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-28 | 2001-08-30 | 2002-03-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-28 | 2005-08-30 | 2006-03-01 | $7700.00 | Window Closed / Lapsed |